PHY-DTR: An Efficient PHY based Digital Transceiver for Body Coupled Communication using IEEE 802.3 on FPGA Platform

Abstract

Body coupled communication (BCC) is an efficient networking approach to body area network (BAN) based on Human-centric communication. The BCC provides interference only between humans in very close proximity. In this work, an efficient Physical layer (PHY) based digital transceiver) is designed for BCC. The digital transceiver Module mainly contains a Digital transmitter (TX) with Manchester encoder, clock synchronization unit, and Digital receiver (RX) with Manchester decoder. The TX and RX modules are designed using a finite state machine as per the IEEE 802.3 Standards. The complete work is also varied for BAN applications by connecting two Application layer transceivers and two Physical layer-based digital transceivers. The architecture is simulated in a Model-sim simulator. The complete Module is synthesized using different FPGA families, and the hardware design constraints are contrasted. The digital transceiver works at 231.28 MHz operating frequency, consumes 0.113W power, and provides a 7.7 Mbps data rate and 4.67 Kbps/Slice efficiency on Artix-7 FPGA. The proposed transceiver is also compared with existing digital transceivers with hardware constraints improvements.

Low-power body-coupled transceiver for miniaturized body area networks

“…The proposed BCC-TR reduces the area overhead of 95.3% for slices, 85.2% for LUTs, frequency of 62.7%, power of 42.4%, and data rate of 77.3% compared to BCC-TR [30]. The PHY-based BCC-TR with Manchester coding (MC) approach [31] is designed on an Artix-7 FPGA. The proposed BCC-TR reduces the area overhead of 81.3% for slices, 69% for LUTs, frequency of 13.5%, power of 1.8%, and data rate of 44.12% compared to the PHY-based BCC-TR [31].…”

“…The PHY-based BCC-TR with Manchester coding (MC) approach [31] is designed on an Artix-7 FPGA. The proposed BCC-TR reduces the area overhead of 81.3% for slices, 69% for LUTs, frequency of 13.5%, power of 1.8%, and data rate of 44.12% compared to the PHY-based BCC-TR [31]. The HBC-TR with FSDT approach [32] is designed on the Artix-7 FPGA.…”