As density of VLSI devices continues to increase at a rapid rate, extensive efforts are being made in development of fine pitch wirebond for IC packages to utilize higher U 0 bonds required for recent fme pitch wirebond applications, the effect of the probe mark under the wirebond ball is counts while shrinking chip sizes. With the small size of ball becoming a major concem for a manufacturable assembly B.ll m d ,mum ?ash process. This paper consists of two portions: a characterization of the current situation and an introduction with experimental analysis of possible solutions.In the fust section, the relationship between probe mark size/depth and the wirebond integrity was evaluated. The evaluation results conclude that the percentage of probe mark area deeper than 0.6um must be limited to 25-30% of the ball bond area to achieve reliable ball bonding.Wafer test however is under continuous pressure to achieve maximum yield results, which often leads to an increase in probe bit frequency and probe mark size. These two conflicting interests are an increasing problem as pad pitch decreases. Conventional AI pads with traditional wirebonding methods will soon be challenged beyond their capabilities if we continue to follow ITRS roadmap. In the second part of this paper, several novel possible pad solutions were investigated and experiments were performed at wafer test and wirebonding.
Part 1: Analysis of Current Wirebond Pad SolutionFine pitch wirebond technology has advanced to meet demand for s W i g chip size and increasing I/O counts over the years. As the bond pad pitch shrinks, the bond pad size and therefore the ball bond diameter and probe mark size also need to shrink. However, the reduction of probe mark sue does not match the rate of reduction in ball bond size as shown in Figure
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