Because of a recent steep drop in the ratio of memory bandwidth to computational performance (B/F) of vector processors, their advantage against scalar ones regarding relatively high sustained performance is decaying. To cover the insufficient B/F rate, an on-chip vector cache mechanism is promising for the vector processors. Although the effectiveness of the vector cache has been evaluated, cache-conscious tuning of vector codes and the analysis of the obtained performance have not been discussed yet. Under this situation, the purpose of this paper is to establish a strategy for performance tuning of a vector processor with a cache to exploit its potential. To analyze its sustained performance, this paper uses the roofline model. Several optimization techniques are applied to real scientific and engineering applications, and their effects are assessed with the model. We confirm that the model can guide users to effective tuning so as to maximize its gain. We also discuss the energy efficiency of the on-chip vector cache.
To realize a high computational efficiency, a 3-D stacked chip multi-vector processor (CMVP) has been proposed. However, the 3-D stacked CMVP has not been evaluated well in terms of energy consumption. Therefore, to clarify the potential of the 3-D stacked CMVP, this paper evaluates and analyzes the energy consumption of the 3-D stacked CMVP using real scientific applications. Especially, this paper focuses on the energy reduction effects given by a large scale vector cache, which can be realized by 3-D die stacking technologies. The evaluation results show the vector cache on the 3-D stacked CMVP has enough potential to achieve a low energy and high performance processing of the cutting edge scientific applications.
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