(La2O3)1-x (Al2O3) x composite films (La2O3:Al2O3 = 100:0, 80:20, 67:33, 50:50) were synthesized using pulsed laser deposition. We investigated their thermal stability and electrical properties as high dielectric constant gate dielectric films. La2O3 (an Al2O3 content of 0%) films were uniformly crystallized as La-silicate after rapid thermal annealing (RTA) at 1000°C for 15 s in an N2 ambient. We found that the addition of Al2O3 suppresses crystallization, and amorphous structures are retained in the samples with an Al2O3 content of 33% or greater. Furthermore, Al2O3 addition suppresses diffusion of Si into upper composite films during RTA. The smallest capacitance equivalent oxide thickness of 1.2 nm was achieved for a sample with an Al2O3 content of 20% and with leakage current density of 3.9×10-3 A/cm2 at + 1 V relative to the flat band voltage.
The mechanism of interface-state generation in metal–oxide–nitride–silicon (MONOS) memories by program/erase (P/E) cycling was experimentally examined, using the charge measurement technique we developed that allows direct measurement of the amount of charges flowing during P/E operation. The amount of interface state was found to have a strong correlation with the amount of charges flowing during erase operation, irrespective of pulse voltage, pulse width and number of P/E cycles. It was also found that the amount of interface states generated by P/E cycling increases as hole fluence dominates erase operation. These findings suggest that hole injection from Si substrate, rather than electron detrapping from SiN layer or impact-ionized hot hole, is the main cause of the interface-state generation.
The relationship between chemical structure (N/Si ratio) or physical structure (laminate structure) of Si-rich nitride charge-trapping layer for MONOS and its electrical characteristics (Program/Erase window, fresh data retention and data retention after Program/Erase cycling stress) are investigated in detail. A laminate structure of Si-rich nitride has been developed that can realize a sufficient Program/Erase window and excellent data retention for MLC operation.
High-k materials, such as HfO 2 and Al 2 O 3 , are known to have dielectric relaxation effect (i.e. slow polarization) [1] [2]. It is reported for the first time in this work that Al 2 O 3 , used as a blocking layer of MANOS NAND flash memory cells, causes modulation of channel current through its dielectric relaxation, resulting in severe transient threshold voltage shift as much as ~ 0.8V. This V th drift cannot be controlled by bit-by-bit verify method, and will severely deteriorate multi-level functionality of NAND flash memory cells. In this work we propose two solutions for this issue. The first one is to give appropriate pre-bias to the word lines of a NAND string before a reading pulse sequence so that the V th drift due to dielectric relaxation can be compensated. The second one is to implement an Al 2 O 3 /SiO 2 /Al 2 O 3 (AOA) stacked blocking layer ( Fig.1(b)) instead of an Al 2 O 3 single layer ( Fig.1(a)). With these solutions, the transient V th drift due to dielectric relaxation can be eliminated entirely. IntroductionMONOS-type NAND flash memory is one of the candidates for future storage systems because of its low cell-to-cell interference [3] and good applicability to 3-dimensional stacked memories [4] [5]. It is common that high-k material such as Al 2 O 3 is used as a blocking layer for suppression of leakage current. However, high-k materials causes dielectric relaxation (slow polarization), and its influence on memory cell characteristics has not been investigated yet. In this work, we evaluate the impact of slow polarization on the V th read-out in a NAND string through measurements of transient drain current in MANOS cells. We also propose solutions to this issue from both architecture and material points of view. ExperimentalIn a NAND string, threshold voltages of each cell are read sequentially by applying a read voltage (V read ) while pass voltages (V pass ) are applied to all the other cells in the same string. Thus, the number of pass-voltage pulses before the read-out event is different from one cell to another. As a good approximation, the state of each cell in a NAND string can be monitored with a single memory cell by applying V pass pulses and measuring drain current as a function of pulse number (Fig.2). Since the reading events repeat in ~10μs periods, high speed I/V converters are connected to the source/drain [6] of a single MONOS transistor, and the source/drain current during gate-pulse application are recorded with an oscilloscope, as shown in Fig.3. Typical samples in the measurement are TaN-gate MANOS transistors with film thicknesses of SiO 2 (4nm)/Si 3 N 4 (5nm)/Al 2 O 3 (15nm), as listed in Table.1. Transient Drain Current in MANOS Transistors due toDielectric Relaxation Transient drain-current characteristics of MANOS memory cells are measured after a step voltage (V meas ) is applied, as shown in Fig.4. This measurement is equivalent to application of 100% duty-ratio pulses, and the maximum impact of dielectric relaxation upon V th drift can be estimated. Fig.5(...
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