In recent years, with the rapid progress of unmanned aerial vehicle (UAV) technology, UAV-based systems have been widely used in both civilian and military applications. Researchers have proposed various network architectures and routing protocols to address the network connectivity problems associated with the high mobility of UAVs, and have achieved considerable results in a flying ad hoc network (FANET). Although scholars have noted various threats to UAVs in practical applications, such as local magnetic field variation, acoustic interference, and radio signal hijacking, few studies have taken into account the dynamic nature of these threat factors. Moreover, the UAVs’ high mobility combined with dynamic threats makes it more challenging to ensure connectivity while adapting to ever-changing scenarios. In this context, this paper introduces the concept of threat probability density function (threat PDF) and proposes a particle swarm optimization (PSO)-based threat avoidance and reconnaissance FANET construction algorithm (TARFC), which enables UAVs to dynamically adapt to avoid high-risk areas while maintaining FANET connectivity. Inspired by the graph editing distance, the total edit distance (TED) is defined to describe the alterations of the FANET and threat factors over time. Based on TED, a dynamic threat avoidance and continuous reconnaissance FANET operation algorithm (TA&CRFO) is proposed to realize semi-distributed control of the network. Simulation results show that both TARFC and TA&CRFO are effective in maintaining network connectivity and avoiding threats in dynamic scenarios. The average threat value of UAVs using TARFC and TA&CRFO is reduced by 3.99~27.51% and 3.07~26.63%, respectively, compared with the PSO algorithm. In addition, with limited distributed moderation, the complexity of the TA&CRFO algorithm is only 20.08% of that of TARFC.
This paper presents a serial multi-channel front-end readout ASIC with a novel architecture and timing control scheme, for the application of flat-panel X-ray, linear detectors and other similar fields. The proposed architecture features the single multi-range selectable integrator, two multiplexed correlated double sampling (CDS) circuits, and the differential buffer output. With the proposed sequential timing control, each channel can output data to the corresponding CDS circuit with no delay when the integration state is ended. So, the channel circuit is simplified. In addition, the proposed architecture and timing control scheme enables the readout ASICs to be cascaded for more channels with tunable conversion rates. To verify the proposed architecture and timing control scheme, a 32-channel readout ASIC was fabricated in TSMC 250nm mixed CMOS signal process. The die size is 2.8 x 2mm 2 . At room temperature, the measured equivalent input noise (EIN) is 25ppm of full-scale value (FSR) with an integration range of 12pC. The measured integral non-linearity is less than 0.04%, and the average power consumption is 2mW per channel. When four ASICs are cascaded, 128 channels are achieved, and a conversion rate over than 30kS/s is measured.
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