This work presents a set of laboratory sessions that can be carried out by students of Digital Design courses required in engineering carrers like Electronics, Communications, Mechatronics, etc. The purpose of these lab is that the students develop their skills and confidence in the design of arithmetic hardware blocks by presenting them specific problems. In this sense, this paper shows a design methodology to be performed in a laboratory for the design of arithmetic blocks which can be implemented in microcontrollers and FPGAs. More specifically, we present the block design of a number's multiplicative inverse (𝟏 𝒙 ⁄ ), its square root (√𝒙) and the square root of its inverse (𝟏 √𝒙 ⁄ ). The completion of these exercises requires the application of the Newton-Raphson algorithm, polynomial approximations of functions, difference equations and digital design. Students of our institution completed the lab sessions and after analyzing the results of student surveys and classroom observations, we found out that completing these tasks significantly contributed to the students' training in the hardware design field.
The Nvidia GPU architecture has introduced new computing elements such as the tensor cores, which are special processing units dedicated to perform fast matrix-multiply- accumulate (MMA) operations and accelerate Deep Learning applications. In this work we present the idea of using tensor cores for a different purpose such as the parallel arithmetic reduction problem, and propose a new GPU tensor-core based algorithm as well as analyze its potential performance benefits in comparison to a traditional GPU-based one. The proposed method, encodes the reduction of n numbers as a set of m × m MMA tensor-core operations (for Nvidia’s Volta architecture m = 16) and takes advantage from the fact that each MMA operation takes just one GPU cycle. When analyzing the cost under a simplified GPU computing model, the result is that the new algorithm manages to reduce a problem of n numbers in T(n) = 5 log_m^2 (n) steps with a speedup of S = 4/5 log (m^2).
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