We describe a scalable protocol for optimizing the quantum cost of the 3-bit reversible circuits built using NCT library. This technique takes into account a group theory approach. The algorithm analyzes the equivalent quantum circuits obtained by decomposing the reversible circuit to its elementary quantum gates and then applies optimization rules to reduce the number of the used elementary quantum gates. We apply the obtained algorithm using different quantum cost metrics that compare favorably with the relevant methods.

Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible R 3 gate to perform the quantum half adder/ subtractor and the quantum full adder/subtractor. The proposed half adder/subtractor design can be used to perform different logical operations, such as AN D, XOR, N AN D, XN OR, N OT and copy of basis. The proposed design is compared with the other previous designs in terms of the number of gates used, the number of constant bits, the garbage bits, 1 the quantum cost and the delay. The proposed designs are implemented and tested using GAP software. keywords:reversible gates; quantum processors; arithmetic unit; reversible adder; reversible subtractor.

We present new algorithms to synthesize exact universal reversible gate library for various types of gates and costs. We use the powerful algebraic software GAP for implementation and examination of our algorithms and the reversible logic synthesis problems have been reduced to group theory problems. It is shown that minimization of arbitrary cost functions of gates and orders of magnitude are faster than its previously counterparts for reversible logic synthesis. Experimental results show that a significant improvement over the previously proposed synthesis algorithm is obtained compared with the existing approaches to reversible logic synthesis.