New Design of Reversible Full Adder/Subtractor Using R Gate

Abstract

Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible R 3 gate to perform the quantum half adder/ subtractor and the quantum full adder/subtractor. The proposed half adder/subtractor design can be used to perform different logical operations, such as AN D, XOR, N AN D, XN OR, N OT and copy of basis. The proposed design is compared with the other previous designs in terms of the number of gates used, the number of constant bits, the garbage bits, 1 the quantum cost and the delay. The proposed designs are implemented and tested using GAP software. keywords:reversible gates; quantum processors; arithmetic unit; reversible adder; reversible subtractor.

A Faster Half Subtractor Circuit Using Reversible Quantum Gates

“…A new reversible half adder/subtractor using R gate was presented in (Montaser et al, 2017). The authors affirm that the quantum cost of this circuit is 4 as they consider each gate as 1 .…”

“…In (Theresal et al, 2015) another half adder/subtractor is presented, with a quantum cost of 7, delay of 7 and 4 inputs. The extra inputs of (Montaser et al, 2017) and (Theresal et al, 2015) are used to switch between addition and subtraction. A similar proposal is presented in (Sarma et al, 2018) with a quantum cost of 5, delay of 5 and 3 inputs.…”

“…However, our proposed circuit shows better results in terms of delay with respect to the other designs of the table. Improvement of F GE * (in %) Design proposed in Delay Quantum Auxiliary Garbage Cost Inputs Outputs (Montaser et al, 2017) 62 25 −50 0 (Theresal et al, 2015) 57 14 0 0 (Murali et al, 2002) 57 14 −50 0 (Thapliyal et al, 2009) 50 0 −50 0 (Das et al, 2017) 50 −14 −50 0 (Sarma et al, 2018) 38 −14 −50 0 (Thapliyal, 2016) 25 −33 −50 0…”

“…The table shows that F GE * implies the use of more quantum gates than (Das et al, 2017, Sarma et al, 2018, Thapliyal, 2016. Moreover, F GE * needs an extra input qubit with respect to (Montaser et al, 2017, Murali et al, 2002, Thapliyal et al, 2009, Das et al, 2017, Sarma et al, 2018, Thapliyal, 2016 to improve the delay. Also, in a similar way to the other approaches, the number of garbage outputs is 0.…”

“…Thus, to develop an efficient subtraction circuit will also benefit a high-performance Shor's algorithm. A half subtractor circuit computes the subtraction of two digits, and there are several works which address it in terms of Quantum Computation (Murali et al, 2002, Thapliyal et al, 2009, Montaser et al, 2017, Theresal et al, 2015, Das et al, 2017, Sarma et al, 2018, Thapliyal, 2016.…”