II. BACKGROUNDWhere, B is the log radix. Plugging (1) into (2) gives the following:(2)(1) =...+C 2R 2 +C1R 1 +CoR o +C_1R-1 +C_ 2R-2 + ...According to the definition, the logarithm of any decimal number, P can be expressed as shown below:Where, R is the numerical base, and C, is the coefficient for the t h power of that base, ranging from 0 to R -1. For decimal base, R equals to 10.The general form of any positive number, L can be expressed as:In this paper, a new method for decimal logarithm (log, in short) computation is presented. The algorithm uses 32-bit floating-point arithmetic, and is based on a digitby-digit iterative computation that does not require error correction circuitry, look-up tables, curve fitting, or division operations. The number of iterations of the log converter depends on the user defined precision. The performance analysis shows that the algorithm produces error-free computation for an internal precision width of 6 digits (24-bit) or more. The architecture is developed using 32-bit binary coded decimal (BCD) representation. The hardware implementation of the logarithmic converter on the Xilinx FPGA has also been presented.In most radix-l0 logarithmic converters, the decimal input is first converted to binary followed by base-2 logarithm computation; after completion, the results are converted back to decimal radix -these back and forth conversions of bases introduce errors on the system. A generalized iterative algorithm to compute base-k logarithm has been presented in [8]; however, the division operation in that work yields erroneous computation. Moreover, the use of lookup tables and the lack of user control on the number of iteration make this algorithm very inefficient for hardware implementation.
AbstractThe paper presents a new and fast algorithm to efficiently compute radix-10 logarithm of a decimal number. The algorithm uses 32-bitfloating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations; the number of iterations depends on the user defined precision. The algorithm produces error-free (infinite precision) results up to 7 decimal digits. A numerical example is shown for the purpose ofillustration. The accuracy is analyzed for several decimal digits showing compliance with the !EEE 754-2008 standard When implemented on to the Xilinx Virtex!! FPGA, the architecture costs only 1,053 logic cells, runs at a maximum frequency of44 MHz, and consumes 79 mW ofpower.
