Manufacturers of modern electronic devices are constantly attempting to implement additional features into ever-increasingly complex and performance demanding systems. This race has been historically driven by improvements in the processor's clock speed, but as power consumption and real estate concerns in the embedded space pose an growing challenge, multithreading approaches have become more prevalent and relied upon. Synchronization is essential to multithreading systems, as it ensures that threads do not interfere with each others' operations and produce reliable and consistent outputs whilst maximizing performance and efficiency. One of the primary mechanisms guaranteeing synchronization in RISC architectures is the load-link/store conditional routine, which implements an atomic operation that allows a thread to obtain a lock. In this study, we implement, test, and manipulate an LL/SC routine in a multithreading environment using GDB. After examining the routine mechanics, we propose a concise implementation in ARMv7l, as well as demonstrate the importance of register integrity and vulnerabilities that occur when integrity is violated under a limited threat model. This work sheds light on LL/SC operations and related lock routines used for multithreading.

<div><div><div><p>In this study, we explored a potential design for a 64-tap 16-bit Finite Impulse Response (FIR) Filter, including several optimizations. We used RTL code, synthesized gate-level netlist, and ran PrimeTime analysis for each component and the overall circuit. We present the methodology associated with this approach, and its operational results. The design chosen uses a 16-bit floating point ALU with a dual-clock, first in first out memory architecture. The final FIR core was functional, as measured via timing and power analysis, throughput, maximum clock frequency, area, error rate, and accuracy. </p></div></div></div>

<div><div><div><p>In this study, we explored a potential design for a 64-tap 16-bit Finite Impulse Response (FIR) Filter, including several optimizations. We used RTL code, synthesized gate-level netlist, and ran PrimeTime analysis for each component and the overall circuit. We present the methodology associated with this approach, and its operational results. The design chosen uses a 16-bit floating point ALU with a dual-clock, first in first out memory architecture. The final FIR core was functional, as measured via timing and power analysis, throughput, maximum clock frequency, area, error rate, and accuracy. </p></div></div></div>