This paper presents a software-hardware based simulation approach to digital system simulation. Our approach provides better performance than a software only approach and also works with high-level system models. The approach uses an optimizing simulation compiler to transform a hardware description language system model into a high performance simulator. The target architecture for the simulation compiler is a tightly coupled processor and field-programmable gate array (FPGA). The components of the simulation compiler are a high performance compiled-code software simulator, an automatic partitioner that partitions the system model between the processor and FPGA, and a scheduler that maximizes concurrent execution within the FPGA and between the FPGA and processor. We describe these components and show how they can be used to improve the performance of synchronous digital system simulation by up to a factor of two when compared to a high performance all software simulator. IntroductionSimulation is used extensively to evaluate performance and to verify correctness of digital systems. As system designs become more complex, the level at which the system is initially specified is made more abstract in order to manage the complexity. Simulation techniques must keep up with these upward shifts in the abstraction level to ensure that systems designers can efficiently evaluate the performance and correctness of their ideas as early as possible in the design process. Recently, there has been a trend towards specifying systems using hardware description languages (HDLs). This trend is partly due to the widespread acceptance of logic synthesis tools and, to a lesser extent, high-level synthesis tools. This trend, coupled with the much greater demand for simulation performance resulting from the increase in system complexity, motivates the need for new simulation techniques that are optimized to simulate high-level system models as efficiently and as economically as possible.In this paper we describe and evaluate a simulation approach that converts an HDL model into a high-performance simulator consisting of tightly coupled software and hardware components that execute on processor and FPGA architecture. Our approach uses compiled-code software simulation, accurate performance estimation, logic synthesis, software-hardware partitioning, and software-hardware scheduling to generate these
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