A decision procedure for a theory of arrays is of interest for applications in formal ver$cation, program analysis, and automated theorem-proving. This paper presents a decision procedure for an extensional theory of arrays and proves it correct.
Bit-v ector theories with concatenation and extraction ha ve been shown to be useful and important for hardware v erication. We h a v e implemented an extended theory which includes arithmetic. Although deciding equality i n s u c h a theory is NP-hard, our implementation is e cient for many practical examples. We believ e this to be the rst suc h implementation which is e cient, automatic, and complete.1 Introduction As designs grow in complexity, design veri cation becomes increasingly important and c hallenging.New and better veri cation techniques are critical to ensure correctness, maintain design cycle times, and protect designers from economic losses due to undiscovered bugs. F ormal methods for verication are especially attractive because they have the potential to co ver most or all of the behaviors in a design without ha ving to exhaustively simulate it.The Stanford Validit y Checker SVC 2, 9 is an automatic veri cation tool whic hhas been in dev elopment for several y ears at Stanford University. The input to SVC i s a Boolean formula in a quanti er-free subset of rst-order logic. It may also contain Boolean operators, uninterpreted functions, and various in terpreted functions suc h as operations on in nite arrays and arithmetic. We h a v e found these constructs to be useful for modeling hardware designs. Using a combination of case-splitting and cooperating decision procedures, SVC determines whether a formula is v alid i.e. equiv alen t to true in ev ery possible interpretation. If the formula is not valid, SVC returns a counterexample. SVC is used as the nal step in the automatic hardware verication paradigm of Burch and Dill 4 . In their approach a speci cation and an implementation are each symbolically sim ulated and the resulting states are then compared to see if they are equivalen t. This method has been shown to be successful for veri cation of actual designs and is currently being applied to the TORCH microprocessor, an aggressive superscalar microprocessor dev eloped for educational and research purposes at Stanford University 11 . The pow erful and e cient decision procedures in SVC are critical for the success of this e ort.Other formal methods such as theorem proving and model checking ha ve been used extensively, but theorem provers su er from a lack of automation and model checking from
We present a new approach to event-driven simulation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those with unclocked feedback and nonunit delay. The elimination of the event queue significantly reduces run-time overhead, resulting in faster simulation. We have implemented our algorithm in a prototype Verilog simulator called VeriSUIF. Using this simulator we demonstrate improved performance vs. a commercial simulator on a small set of programs.
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverage metrics are essential to guide the development of effective test suites. Traditional coverage metrics are defined based on either a functional model or a structural model of the design. If our goal is to select a subset of tests from a set of tests, using these coverage metrics require simulation of the entire set before the effectiveness of tests can be compared. In this paper, we propose a novel methodology that estimates the input space covered by a set of tests. We use unsupervised support vector analysis to learn such a space, resulting in a subset of tests that represent the original set of tests. A direct application of this methodology is to select tests before simulation in order to reduce simulation cycles. Consequently, simulation effectiveness can be improved. Experimental results based on application of the proposed methodology to the OpenSparc T1 processor are reported to demonstrate the practicality of our approach.
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