Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. Hierarchical scene matching is a technique for reducing the amount of computation involved an scene matching applications. Most of the past research on this problem has concentrated on efficient soflware algorithms, and very little effort has been ezpended on custom hardware solutions. In this paper, we propose a new VLSI architecture for Hierarchical Scene Matching. The proposed architecture achieves a significant amount of speedup by utilizing a large amount of parallelism and pipelining.
Scene rnatchzng as the problem oj matching regzons oftwo images ofthe same scene taken by different sens'ors at different tim,es or under different viewing conditions. Hierarchical scene matching is a technique for reducing the amount of computation involved in scene matching applications. Most of the past research on this problem has concentrated on efficient software algorithms, and very little effort has been expended on custom hardware solutions. In this paper, we describe the design of SMAC, a new VLSI architecture for Hierarchical Scene Matching. This architecture achieves a sign,ijicant amount of speedup by utilizing a large amount of parallelasm and pipelining. The paper also describes the design and implementation of a prototltype CMOS VLSI d i p that implements the exhaustive scarch task of the scene matching algorithm.
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