SMAC: A VLSI Architecture for Scene Matching

Ranganathan, N.; Sastry, R.; Venkatesan, R.

doi:10.1006/rtim.1998.0093

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Cited by 3 publications

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“…The proposed architecture is a single pixel processor and, thus, it avoids the performance bottlenecks related to the external bus and memory access that are associated with other, parallel architectures [7,8]. Also the proposed architecture produces very satisfactory frame rate results when compared to other, similar architectures [9,10].…”

Section: Introductionmentioning

confidence: 55%

“…Additionally, since the proposed CA architecture processes each pixel in turn, it avoids the performance bottlenecks related to the external bus and the memory access that are associated with other, parallel processing architectures [7,8]. Also, the proposed architecture completely avoids multiplication paths which play a critical role in the performance of RISC architectures for image processing [7].…”

Section: P Tzionasmentioning

confidence: 96%

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