The effects of Ti incorporation in a Ni film on the silicidation reaction as well as the structural and electrical properties of NiSi have been investigated. Experimental results from this work showed that the reaction-inhibiting effect of an interfacial oxide layer could be effectively overcome by Ti incorporation. It was found that, in the presence of a thin interfacial oxide ͑1-2 nm͒, the onset of the silicidation reaction occurs at 300°C with a Ni͑5 atom % Ti͒ alloy while the thin interfacial oxide effectively delays the silicidation reaction up to 700°C for pure Ni. It was found that Ti reacts with the interfacial oxide, yielding an altered oxide layer, which acts as a Ni-permeable diffusion membrane during silicidation. In addition to the dramatic effect on the interfacial reaction during silicide formation, Ti incorporation was also found to improve morphological and thermal stability of NiSi. As a result, Ni͑Ti͒-silicided p ϩ /n diodes ͑with/without an interfacial oxide͒ showed an improvement in junction integrity, as compared to pure Ni-silicided p ϩ /n diodes. It is believed that the ability to form silicide effectively even in the presence of an interfacial oxide, coupled with improved junction integrity, will greatly relieve constraints on processing conditions and significantly enhance manufacturing yield.The use of metallic silicides to reduce the gate and source/drain contact resistance is crucial in achieving high-speed device operation in advanced complementary metal oxide semiconductor ͑CMOS͒ devices. Recently, NiSi has been shown to be an attractive alternative to currently used silicides, i.e., TiSi 2 and CoSi 2 , for future 0.1 and sub-0.1 m generation CMOS devices due to its high conductivity, large processing window, low Si consumption, and ability to maintain low resistivity even for linewidths down to 0.1 m. 1-4 However, a number of process/integration issues, such as the sensitivity of NiSi formation to oxygen impurities ͑e.g., residual oxide on Si surface͒, 5 remain to be addressed and resolved before the full implementation of NiSi process in future sub-0.1 m generations of CMOS devices is realized.It is known that, like CoSi 2 , 6-9 the formation of NiSi is substantially suppressed or even completely inhibited if a thin interfacial oxide is present. 9 For example, it was reported that the presence of a thin native oxide effectively delays the formation of Ni-silicide up to 800°C. 10 This sensitivity of NiSi formation to the interfacial oxide often results in the formation of a rough silicide/Si interface, when the initial Si surface is partially oxidized, or even a complete failure to form NiSi if the initial Si surface is fully oxidized. While the failure to form NiSi would directly result in unacceptably high contact resistance on source/drain and gate regions, the formation of rough silicide/Si interface has been identified as the primary cause for anomalously large junction leakage on shallow junctions. 11 In addition, it has also been shown that NiSi is extremely sensitive to oxy...

The results of this study demonstrate the viability of a low cost maskless process for the fabrication of ultra-fine pitch solder bumps. The fabricated solder bump arrays have a pitch and diameter of 120 and 70 μm, respectively. Widely used eutectic 63Sn37Pb and lead-free 95.5Sn3.8Ag0.7Cu solders were used to form the bumps. No solder bridging was observed between adjacent bumps, and the solder bumps exhibited good dimensional uniformity. The solder bump to aluminum (Al) pad bond integrity was found to be excellent, as evidenced by the high stress to failure. The failure mode is predominately Al pad lift-off indicating a robust solder bump-pad joint.