With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-the-field faults. To be broadly deployable, the hardware reliability solution must incur low overheads, precluding use of expensive redundancy. We explore a cooperative hardware-software solution that watches for anomalous software behavior to indicate the presence of hardware faults. Fundamental to such a solution is a characterization of how hardware faults in different microarchitectural structures of a modern processor propagate through the application and OS.This paper aims to provide such a characterization, resulting in identifying low-cost detection methods and providing guidelines for implementation of the recovery and diagnosis components of such a reliability solution. We focus on hard faults because they are increasingly important and have different system implications than the much studied transients. We achieve our goals through fault injection experiments with a microarchitecture-level full system timing simulator. Our main results are: (1) we are able to detect 95% of the unmasked faults in 7 out of 8 studied microarchitectural structures with simple detectors that incur zero to little hardware overhead; (2) over 86% of these detections are within latencies that existing hardware checkpointing schemes can handle, while others require software checkpointing; and (3) a surprisingly large fraction of the detected faults corrupt OS state, but almost all of these are detected with latencies short enough to use hardware checkpointing, thereby enabling OS recovery in virtually all such cases.

There is evidence to recommend the use of exercise training as an adjunct to medical treatment in PAH. More clinical trials and research are required to assess the effects of different types of exercise programs in patients with PAH, while focussing on strong exercise endpoints to quantify the improvements seen with exercise training.

The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chips. Extremely complex, massively parallel, multi-core processor chips fabricated in these technologies will become more vulnerable to: (a) environmental disturbances that produce transient (or soft) errors, (b) latent manufacturing defects as well as aging/wearout phenomena that produce permanent (or hard) errors, and (c) verification inefficiencies that allow important design bugs to escape in the system. In an effort to cope with these reliability threats, several research teams have recently proposed multicore processor architectures that provide low-cost dependability guarantees against hardware errors and design bugs. This paper focuses on dependable multicore processor architectures that integrate solutions for online error detection, diagnosis, recovery, and repair during field operation. It discusses taxonomy of representative approaches and presents a qualitative comparison based on: hardware cost, performance overhead, types of faults detected, and detection latency. It also describes in more detail three recently proposed effective architectural approaches: a software-anomaly detection technique (SWAT), a dynamic verification technique (Argus), and a core salvaging methodology.

Introduction Theoretical risks of biologic agents remain under study. Objective The aim of this study was to integrate 1-year safety data from 12 ustekinumab registrational trials. Methods Patients had moderate-to-severe plaque psoriasis, active psoriatic arthritis (PsA) (± methotrexate), or moderate-to-severe Crohn’s disease (CD; failed/intolerant of immunomodulators/corticosteroids). Psoriatic patients received subcutaneous ustekinumab 45/90 mg or placebo, generally at week 0, week 4, then every 12 weeks thereafter, while those with CD received a single intravenous ustekinumab dose (130 mg or weight range-based dosing of approximately 6 mg/kg) or placebo induction dose at week 0, followed by subcutaneous ustekinumab 90 mg at week 8 and every 8/12 weeks thereafter. The incidence rates of a priori-defined safety events were integrated post hoc (adjusted for duration of follow-up, reported per 100 patient-years [PYs]). Results Among 6280 enrolled patients, 5884 ustekinumab-treated patients (psoriasis: 3117; PsA: 1018; CD: 1749) contributed 4521 PYs versus 674 PYs in placebo-treated patients through year 1 (829 PYs and 385 PYs during 8- to 16-week controlled periods). Combined across diseases among ustekinumab- versus placebo-treated patients, respective incidences/100 PYs (95% confidence intervals) of infections were 125.4 (122.2–128.7) versus 129.4 (120.9–138.3) through year 1, and not meaningfully increased in patients who did versus those who did not receive methotrexate (92.5 [84.2–101.5] vs. 115.3 [109.9–121.0]), or significantly increased in patients who did versus those who did not receive corticosteroids (116.3 [107.3–125.9] vs. 107.3 [102.0–112.8]) at baseline. Major adverse cardiovascular events (0.5 [0.3–0.7] vs. 0.3 [0.0–1.1]), malignancies (0.4 [0.2–0.6] vs. 0.2 [0.0–0.8]), and deaths (0.1 [0.0–0.3] vs. 0.0 [0.0–0.4]) were rare across indications. Conclusions Ustekinumab demonstrated a favorable and consistent safety profile across registrational trials in approved indications. Trial Registrations ClinicalTrials.gov identifier: NCT00320216, NCT00267969, NCT00307437, NCT00454584, NCT00267956, NCT01009086, NCT01077362, NCT00265122, NCT00771667, NCT01369329, NCT01369342, and NCT01369355.

Objectives The objective of this study was to assess the effects of home-based exercise training (HBET) on function and quality of life (QoL) in patients with pulmonary hypertension (PH). Methods A prospective, nonblinded, randomized clinical trial was carried out on 84 medically stable patients with PH belonging to any functional class or etiology and of either sex. Patients were randomized to either standard care or HBET. Both groups also received education using the Pulmonary Hypertension Manual (PulHMan). Outcomes included functional capacity from 6-min walk distance (6MWD), QoL using the Medical Outcomes Survey Short Form – 36, functional class (FC), and right heart indices (right ventricular systolic pressure [RVSP] and tricuspid annular plane systolic excursion [TAPSE]) and were assessed at entry and after 12 weeks. Results HBET improved 6MWD by 48.5 m and 13 m in the experimental and control groups, respectively ( p < 0.001). QoL showed statistical improvements after HBET between the groups for the physical and mental components and for the various subdomains (except body pain). Furthermore, FC improved by one grade with HBET ( p < 0.001). Conclusion HBET program improved functional capacity, QoL, and FC in patients with PH.

In the near future, hardware is expected to become increasingly vulnerable to faults due to continuously decreasing feature size. Software-level symptoms have previously been used to detect permanent hardwarefaults. However, they can not detect a smallfraction offaults, which may lead to Silent Data Corruptions(SDCs). In this paper, we present a system that uses invariants to improve the coverage and latency of existing detection techniques for permanent faults. The basic idea is to use training inputs to create likely invariants based on value ranges of selected program variables and then use them to identifyfaults at runtime. Likely invariants, however, can have false positives which makes them challenging to use for permanent faults. We use our on-line diagnosis framework for detecting false positives at runtime and limit the number offalse positives to keep the associated overhead minimal. Experimental results using microarchitecture level fault injections in full-system simulation show 28.6% reduction in the number of undetected faults and 74.2% reduction in the number of SDCs over existing techniques, with reasonable overheadfor checking code.

Abstract

As devices continue to scale, future shipped hardware will likely fail due to in-the-field hardware faults. As traditional redundancy-based hardware reliability solutions that tackle these faults will be too expensive to be broadly deployable, recent research has focused on low-overhead reliability solutions. One approach is to employ lowoverhead ("always-on")