Architectures for online error detection and recovery in multicore processors

Abstract

The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chips. Extremely complex, massively parallel, multi-core processor chips fabricated in these technologies will become more vulnerable to: (a) environmental disturbances that produce transient (or soft) errors, (b) latent manufacturing defects as well as aging/wearout phenomena that produce permanent (or hard) errors, and (c) verification inefficiencies that allow important design bugs to escape in the system. In an effort to cope with these reliability threats, several research teams have recently proposed multicore processor architectures that provide low-cost dependability guarantees against hardware errors and design bugs. This paper focuses on dependable multicore processor architectures that integrate solutions for online error detection, diagnosis, recovery, and repair during field operation. It discusses taxonomy of representative approaches and presents a qualitative comparison based on: hardware cost, performance overhead, types of faults detected, and detection latency. It also describes in more detail three recently proposed effective architectural approaches: a software-anomaly detection technique (SWAT), a dynamic verification technique (Argus), and a core salvaging methodology.

Defect tolerance: Fundamental limits and examples

“…This side information enables significant savings in redundancy [13]. In fact, this method of testing the performance of a device followed by some configuration is rather popular in practice, used in multi-core CPUs [14], analog-to-digital converters [15], sense-amplifiers [16], selfreplicating automatons [17], parallel computing [18], [19], etc. This paper can be seen as an attempt to provide theoretical foundations for the static defect scenario.…”

“…In particular, for t = 2, we can first choose ε = 3/2. No matter how we choose the values of π 2 , π 3 and π 4 , to satisfy (14) we must have ρ ≥ 1/2.…”

Stochastic testing of processing cores in a many-core architecture

“…These many-core architectures have opened new horizons in microprocessor industry and are going to be a dominant trend in general purpose microprocessors [1][2][3][4][5], and also in specialized processing units such as Graphics Processing Units (GPUs) and Network Processing Units [6,7]. However, extensive miniaturization and large scale integration in new fabrication technologies have led to unpleasant side effects such as production yield drop, infant mortality, and accelerated aging [8][9][10] in all nano-scale semiconductor devices including many-core processors. In fact, because of non-aggressive burn-in testing, more pronounced aging effects, and incomplete testing and verification processes due to increased time-to-market pressure in new fabrication technologies, systems fabricated in these technologies may experience faults (including early defects or latent faults) and fail any time in the field.…”

On the field design bug tolerance on a multi-core processor using FPGA

“…Other types of design defects that are not complicated can be fixed by the extensive testing that happens on the manufacturing side (Gizopoulos et al, 2011). With the above design bugs, there can be four classifications:…”

“…Fault isolation using hardware and software codesign is done by Khan and Kundu (2010). Isolating defects at various levels is explained in detail by Gizopoulos et al (2011). In design bugs related fault isolation, the exact location of faults and the context of the faulty event should be narrowed down.…”