A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low power applications is presented in this review. The topics discussed include subthreshold operation in FET devices, micro-currentmirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductancecapacitance and log-domain filters and strained-channel FET technologies.1

Abstract-A novel large-signal transimpedance amplifier frontend, intended for monolithic integration with a Si p-i-n diode and employing HBT-CMOS technology for use in short-range optoelectronic interconnects is proposed. Simulated bandwidth and gain are 4 Gbits/s and 43 dB, respectively, while driving a 100-fF load to TTL voltage levels.

An MOCVD-grown circular geometry InP/InGaAs double heterojunction bipolar transistor utilizing a novel δ + -layer composite collector structure was fabricated. A breakdown voltage of 12 V and an offset voltage of just 100 mV were achieved and high injection current densities over 3.2 × 10 5 A cm −2 , which suggest no significant current blocking related to the wide bandgap InP collector layers. A cut-off frequency of 42 GHz was measured at a collector current density of 1.1 × 10 6 A cm −2 .

An MOCVD-grown circular geometry InGaP/GaAs double heterojunction bipolar transistor with a novel δ + -layer composite collector structure was fabricated. A breakdown voltage of 13 V and an offset voltage of just 110 mV were achieved as well as high injection current densities over 3.2 × 10 5 A cm −2 , which suggest no significant current blocking related to the wide bandgap InGaP collector layers. A cut-off frequency of 35 GHz was measured at a collector current density of 2.4 × 10 5 A cm −2 .

Circular geometry InGaP/GaAs double heterojunction bipolar transistors with spacings of 94.5, 44.5, 19, 10.5 and 5.5 µm between the base metal and emitter mesa were fabricated and characterized. The measured Gummel plots showed a current gain of 50 for the 94.5 µm device. As the spacing decreases to 5.5 µm, the base current increases due to the extrinsic base surface recombination current at V BE = 0.9 V thus reducing the current gain to a value of 10. It was found that the use of Ti/Au over Au/Zn/Au base metallization schemes eliminates this recombination current component of the base thereby improving the current gain significantly to 100. With a novel scheme employed here termed the δ + -layer composite collector structure, the collector leakage current was investigated.