The spin coherence time (T2*) in ZnO single crystals at 8.5 K decreases significantly from ∼11.2 ns to ∼2.3 ns after annealing at 500 °C, as indicated by time-resolved Kerr-rotation pump-probe magneto-optical spectroscopy. The annealing-induced spin coherence degradation in ZnO arises neither from crystallinity degradation during the annealing process, as confirmed by x-ray rocking curves; nor from reflection variations of the probe laser beam induced by surface roughness changes during the annealing process, as confirmed by atomic force microscopy. Temperature-dependent Hall-effect studies indicate that decreased mobility and increased shallow-donor concentration in the annealing-induced surface conducting layer on top of the bulk ZnO are most likely to be the reasons for the spin coherence degradation in ZnO during the annealing process.
A single-crystalline Si film was transferred onto a Si wafer and non-alkaline glass by hydrogen-induced exfoliation and the effect of pulsed green-laser annealing was investigated. Above a laser energy of 1285 mJ/cm 2 , the crystallinity of the Si film was recovered both on the Si wafer and the glass. The linewidth of micro-Raman spectra of the Si film on the Si wafer was constant at about 3.9 cm À1 which was close to that for commercial silicon-on-insulator (SOI) wafer. On the other hand, the linewidth of the Si film on the glass was constant at about 4.1 cm À1 . A Raman peak shift toward a lower frequency was observed on the Si film on the glass; it was assumed that the difference of the linewidth on the Si wafer and that on the glass originated from the tensile stress in the Si film due to the difference of thermal expansion coefficients. The results of numerical simulation suggested that the thickness of the region damaged by hydrogen ion implantation was greater than 300 nm; the damaged region had to be melted and resolidified to obtain the recovered single-crystalline silicon upon pulsed laser annealing.
Low-temperature (350 C) and high-pressure (1 MPa) steam annealing is effective for improving the characteristics of lowtemperature-processed polycrystalline silicon thin film transistors (LTPS-TFTs) and their uniformity. We developed highpressure annealing systems for 600 Â 720 and 400 Â 500 mm 2 glass substrates, and investigated the annealing effects on the electrical properties of n-channel TFTs. The TFTs fabricated without high-pressure annealing have a low saturation mobility caused by the large amount of fixed oxide charge in SiO 2 , and a high threshold voltage (V th ) caused by the high trap density at the SiO 2 /Si interface. High-pressure steam annealing effectively reduces the amount of fixed oxide charge and the number of interface traps, resulting in the improvement of TFT properties. The crystal orientation of poly-Si strongly affects the interface trap density, which causes the nonuniformity of the TFT characteristics. High-pressure annealing also decreases the deviation of the trap density caused by the crystal orientation, and uniform electrical properties are achieved.
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