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In this paper we present both finite element based and analytic model simulations of pentacene based organic thin film transistor. The finite element type simulation is done using Silvaco's Atlas simulator and the analytic model simulation is performed using a Matlab code based on the standard transistor equations. Both the Atlas and Matlab simulations agree approximately with the published experimental result. The results of the simulations show a current ratio of 2.11 × 10 6 for Atlas and 1.8 × 10 7 for Matlab simulations. The threshold voltage extracted from the finite element type simulation is 1.1 V which is in good agreement with 1.2 V used for Matlab simulation. However, the contact resistance shows a quite significant variation between the two simulation mechanisms. The finite element type simulation gives a contact resistance of 10 k whereas the Matlab simulation predicts a contact resistance 1.9 k .

An exact analytical solution for the plane wave reflection coefficient in an isotropic, constant velocity medium exhibiting an exponential impedance space profile is derived. The analysis includes the effects of discontinuities at both boundaries of the impedance transformer. The derivation is based on an exact differential equation that describes the space evolution of the reflection coefficient along a nonuniform transmission line. Power transmission curves for various cases, including the exact quarterwave case, are presented.

Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole-Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9 dB and 29.7 dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor.

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