Significant power reduction can be achieved by exploiting realtime variation in system characteristics while decoding convolutional codes. The approach proposed herein adaptively approximates Viterbi decoding by varying truncation length and pruning threshold of the T-algorithm while employing trace-back memory management. Adaptation is performed according to variations in signal-to-noise ratio, code rate, and maximum acceptable bit error rate. Potential energy reduction of 70 to 97.5% compared to Viterbi decoding is demonstrated. Superiority of adaptive T-algorithm decoding compared to fixed T-algorithm decoding is studied. General conclusions about when applications can particularly benefit from this approach are given.
A novel approach is introduced that exploits characteristics of fixed-point, two's complement data in order to reduce power consumption related to switching activity. This approach is based on an intuitive switching activity model that captures the most essential data characteristics with statistical parameters. The approach is embodied in a heuristic that uses the model to systematically reduce switching activity of interconnect between datapath units. The perspective provided by the model and heuristic allows efficient and intuitive high-level design space exploration. This approach is demonstrated through an example of high-level design space exploration for a low power processor dedicated to implementing the IS-54 vector-sum excited linear predictive (VSELP) speech codec. Application of the heuristic results in up to 56% activity reduction at high energy locations in the datapath and estimated processor power reduction of about 15% on average during encoding compared to an obvious implementation.
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