Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations

Abstract

Significant power reduction can be achieved by exploiting realtime variation in system characteristics while decoding convolutional codes. The approach proposed herein adaptively approximates Viterbi decoding by varying truncation length and pruning threshold of the T-algorithm while employing trace-back memory management. Adaptation is performed according to variations in signal-to-noise ratio, code rate, and maximum acceptable bit error rate. Potential energy reduction of 70 to 97.5% compared to Viterbi decoding is demonstrated. Superiority of adaptive T-algorithm decoding compared to fixed T-algorithm decoding is studied. General conclusions about when applications can particularly benefit from this approach are given.

An Efficient Viterbi Decoder Architecture

“…have two paths, ending a given state. As these are 2 k-1 encoder states in a survivor paths at any given time [7].…”

“…The puncturing matrix is applied to the output stream. This is done in BMU to correct a low capable errors [7]. The serial bits stre3am in BMU is doing by shift registers.…”

A game theoretic approach to dynamic energy minimization in wireless transceivers

“…In Adaptive Viterbi Algorithms (AVA), developed in [7][8][9], the decoding performance is increased by reducing the number of operations required to decode a single bit. This is achieved by reducing truncation length (TL) or by reducing the number of survivor paths¸ i.e., those paths that are kept in order to find the optimum path.…”

“…More recently, in [7], power consumption of a high memory-order punctured convolutional decoder has been reduced by using an adaptive algorithm based on the channel bandwidth and the received SNR, thereby, reducing the required energy for decoding a single bit of information. All of the aforementioned techniques for energy reduction in communication systems (implicitly or explicitly) assume that the baseband and pass-band transceivers are independent.…”

Low-Power-Adaptive MC-CDMA Receiver Architecture

“…It is possible to reduce the power consumption further by dynamically reducing the complexity of the receiver architecture in real time as per the changing channel requirements like the delay spread, signal-to -noise ratio (SNR), bandwidth, bit error rate and so on. In [5], the authors have achieved power saving in a Viterbi decoder by dynamically varying its architecture according to real-time changes in system characteristics. This paper proposes altering the FFT size or inverse FFT (IFFT) size in real time as per the channel delay spread instead of using a fixed large FFT-based transceiver designed for the worst-case delay spread.…”