Proposed work presents high performance architecture for LILI-II stream cipher. This cipher uses 128 bit key and 128 bit IV for initialization of two LFSR. Proposed architecture uses single clock for both LFSRs, so this architecture will be useful in high speed communication applications. Presented architecture uses four bit shifting of LFSR D in single clock cycle without losing any data items from function F C . Proposed architecture is coded by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and targeted hardware is Xilinx Virtex5 FPGA having device xc4vlx60, with package ff1148. Proposed architecture achieved throughput of 224.7 Mbps at 224.7 MHz frequency.
General TermsHardware implementation of stream ciphers
In wireless ad-hoc network energy of node is very important issue. Less amount of energy is directly affect the lifetime of network because all nodes in networks are battery operated devices. So optimization of energy consumption in network has greater impact on network life. The power consumption can be reduced at node level, transmission and receiving level. This paper is focusing on how various propagation models affect the energy consumption in ad-hoc network with MANET routing protocols. The four widely used Ad-hoc routing protocols compared are: Ad-hoc on demand Distance Vector (AODV), Destination Sequenced Distance Vector (DSDV), Dynamic Source Routing (DSR), and Ad-hoc on demand Multipath Distance Vector (AOMDV). Simulation has been carried out using Network Simulator 2.34 and its associated tools like Network Animator.
Modulo (2 31 -1) adder is one of the important module in ZUC stream cipher. The paper presents compact, high performance architecture for modulo (2 31 -1) adder using CLA. The proposed architecture is implemented by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and target device is Xilinx Spartan3-xc3s1000, with package FG320. Presented result shows that proposed architecture minimizes the chip area, power consumption and increases computation speed of modulo (2 31 -1) adder.
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