The main practical application behind the development of chitosan (CH) and O-carboxymethyl chitosan (CMC) used to preserve postharvest whiteleg shrimp lies with the fact that these polysaccharides represent a renewable source of natural biodegradable polymers and meet with the emergence of more and more food safety problems. Both CMC and CH can be used as food preservatives to extend shrimp shelf life. However, CMC is more convenient due to its solubility. In the future, CMC will be used in the food processing industry because of its soluble, compatible, antimicrobial, and antioxidative characteristics.

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This paper proposes a low-power delta-sigma capacitance-to-digital converter (CDC) for a capacitive sensor. The input of the capacitive sensor employs a zoomed-in technique with the offset capacitor to extend the input capacitance range. The proposed CDC uses a third-order switched capacitor deltasigma modulator to provide a digital output, based on a cascade of integrators with a feed forward (CIFF) structure. The current-starved operational transconductance amplifiers (OTAs) are applied in the delta-sigma modulator's first integrator to improve the current efficiency and reduce the power consumption. An autozeroing technique is used in the OTAs to reduce their offset and noise. The circuit was implemented in a 0.18-µm CMOS technology and occupies an area of 0.496 mm 2. The measurable capacitance range of the CDC can be varied from 0 to 8 pF. In a measurement time of 0.8 ms, the delta-sigma CDC achieved a 12.7 effective number of bits while consuming 18.6-µA current from a 2-V supply voltage. INDEX TERMS Capacitive sensors, delta-sigma modulation, low power.

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Current osteochondral (OC) defect repair approaches using premade scaffolds face clinical limitations due to invasiveness, weak integrity, and/or insufficient interfacial bonding. An injectable hydrophobic laminous adhesive is developed that rapidly photocross‐link subaqueously and forms robust bi‐layered structure that orchestrates biophysical‐chemical cues for stimulating OC repair. Liquid hydrophobic photo‐cross‐linkable poly (lactide‐co‐propylene glycol‐co‐lactide) dimethacrylates (PmLnDMA) are adopted as cartilage phase and PmLnDMA encapsulating methacrylated hydroxyapatite nanoparticles (PmLnDMA/MH) as the mineralized subchondral bone phase. Both phases exhibit strong interfacial bonding due to the presence of “CC”. Mechanotransduction and growth factor‐mediated signaling pathways are enchanced by matching the mechanical properties of two phases to native cartilage and bone via systematical modulation of the adhesives’ composition and encapsulated growth factors’ release profile. This enhances mesenchymal stem cells’ commitment to corresponding chondrocytes and osteoblasts to augment OC repair in vitro and in vivo, and ultimately benefits patients suffering from OC fracture, osteoarthritis, and osteoporosis.

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This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of ±0.11 °C (3σ), exceeding the accuracy of ±0.23 °C (3σ) achieved without calibration. We implement the sensor in a 0.18 µm CMOS process, occupying an area of 0.42 mm2. It achieves a resolution of 0.01 °C and has a conversion time of 24 ms.

To reduce the power consumption of a bio-electrical signal detection system, a level-crossing analog-to-digital converter (LC-ADC) with low power consumption was proposed for biomedical signal detection. An adaptive resolution sampling mode is also designed to reduce power consumption on the original basis. The level-crossing ADC is designed and simulated using a 180-nm CMOS process. The measurement results show that the power consumption is only 197 nW, the effective number of bits is 6.4 bits and the signal-to-noise and distortion ratio is 41.6 dB under 0.8 V power supply voltage. The proposed LC-ADC uses a chip area of 0.147 mm 2 and the FOM is 278 fJ/conversion.