DDR3 memory interface (I/F) with single-end signals is very sensitive to external environments, such as chip package type and system board design. In order to guarantee the system performance, IP providers often define the package and PCB design constraints to reduce product risks [1]. These design constraints may increase the package size and DDR3 PCB area to cost, increasing the whole system cost. Therefore, our DDR3 memory I/F design addresses this problem, relaxing the external environment requirements, especially relating to power integrity, and achieves 2.667Gb/s operation in a wirebond package and singleside mounted PCB. The difference between double-side and single-side mounted PCB is shown in Fig. 26.6.1. The capacitor on the PCB cannot be mounted directly near the SOC on the back side of PCB. This external environment increases the distance of the current return loop and also increases the inductance of power decouple capacitance equivalently. General DDR3 memory interface is shown in Fig. 26.6.2(a). In the output stage, data signal traverses a programmable delay line, connects to level-shift-up circuit and then drives via the output driver. The supply bounce in DDR3 I/O 1.5V affects the output jitter so that the circuit speed and supply-noise generation of level-shift-up circuit and output driver are key factors. One method of output stage improvement is realized in the output driver by cascoded thin-gate-oxide device [2][3]. This method can reduce the latency of the output driver stage and reduce transient supply noise in its I/O power domain. However, it needs an additional overshoot/undershoot sense circuit [2] to decrease the risk of device reliability or lifetime issues and it also increases circuit complexity.Our output driver is implemented using thick-gate-oxide devices to avoid the device reliability problem. The traditional level-shift-up circuit is sensitive to supply noise since the speed of thick-gate-oxide devices is not fast enough, especially in 2.5V I/O device process. Therefore, the clocking-based levelshift-up circuit with 2-1 serializer is designed to speed up the signal transition from the core power domain to the I/O power domain. In addition, the programmable-delay circuit is moved from the data path to clock path as shown in Figs. 26.6.2(b) and 26.6.2(c). The traditional programmable-delay circuit in the data path may suffer from supply noise and result in the data jitter increasing. An internal LDO can be implemented to suppress the supply noise but the capacitor area must be large enough to cover broadband data transition noise. In our method, the delay cell is moved to the clock path and its internal LDO design can be implemented easily without consideration for broadband data transition noise. Therefore, the output jitter of transmitter from supply noise is minimized.Moreover, the power dissipation of SoC in home entertainment devices, such as DTV or DVD player, make it important to relax the thermal-resistance specification of chip package. Figure 26.6.3(a) shows the simpli...
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