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Summary DC‐DC converters are conventionally utilized to drive DC motors, where boost converters are employed in several emerging drive‐based applications. The modern boost converter motor drives are controlled with digital circuits due to its flexibility and cost‐effectiveness. However, the impact of the sampling in digital controllers is generally neglected during the modeling of the drives. In this paper, the sampling effect of digital controllers is analyzed for the steady‐state speed of the boost converter fed brushed permanent magnet DC (PMDC) motor drive, and the corresponding mathematical model is proposed. A relationship is established between time delay, multisampling factor, and duty ratio, which is further implemented on the PMDC motor model. The modeling shows that a time delay in pulse generation is induced due to the sampling that changes the duty ratio and the resultant motor speed. The variation in motor speed obtained from the analysis justifies the relevance of the proposed model. The proposed mathematical model shows that a high sampling frequency of the digital controller is essential to adapt the analog controller‐based motor drive behavior. However, an optimization methodology between the controller frequency and drive performance for low‐cost applications has been mentioned in this paper. The experimental analysis performed on the simulation environment and the real‐time laboratory prototype complements the precision of the proposed model.

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SummaryA dual‐duty digital pulse‐width modulation (DDPWM) technique‐based cost‐effective control hardware architecture for brushless DC (BLDC) motor drive is reported in this paper. DDPWM control technique involves reduced computational complexity, which is beneficial in on‐chip area and power dissipation reduction. Simple Hall sensor‐based speed calculation and commutation circuits were also incorporated in the hardware to reduce the chip area further. The edge detection‐based speed calculation circuit was designed to be tolerant of any external noise or glitch in the Hall sensor signal. The proposed hardware architecture was implemented on the field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC) platform using TSMC 180‐nm technology library. The ability of the integrated circuit (IC) for resource utilization reduction was validated by comparing the FPGA‐implemented architecture with the existing literature. The FPGA‐implemented architecture was also examined in real‐time using an experimental prototype BLDC motor setup. The drive response with dynamic load and speed variations, speed control precision, and glitch tolerant speed calculation is reported in the paper. The ASIC implementation demonstrates that the developed architecture sampled at 50 MHz is highly effective in the gate count and power dissipation reduction compared to the standard PI controller‐based width modulated pulse generation hardware architecture.