In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace Tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.
Double Stage Differential Amplifier comprises many advantages by operating differential inputs. It provides excellent immunity to external noise which is certainly a flawless advantage for low-power devices and also reduces Low-Order Harmonics (LOH). This paper presents the design of a double stage differential amplifier using Carbon Nanotube Field Effect Transistors (CNTFETs). The key approach of the proposed design is to reduce the Total Harmonic Distortion (THD), Low-Order Harmonics (LOH), output delay and to achieve a high trans-conductance gain, gm. The paper also carries the significant comparisons between conventional differential amplifier and the proposed design. Both circuits have been simulated by using HSPICE model of CNTFET. The optimized threshold voltage is 0.309V and given bias is 1V only. The Fast Fourier Transform (FFT) and Fourier analysis also shows an outstanding result compared to the conventional one. Moreover, the output voltage is closely zero at common-mode operation which yields a very high Common-Mode Rejection Ratio (CMRR). From the analysis in both common-mode and differential-mode inputs the proposed design was proven to be robustly noise-immune.
Abstract-This paper presents a high frame rate capable Active Pixel Sensor (APS) using Carbon Nanotube Field Effect Transistor (CNTFET) instead of Complementary Metal Oxide Semiconductor (CMOS). Conventionally, the design of a single APS circuit is based on three transistors (3T) model. In order to achieve higher frame rate, one extra transistor with a column sensor circuit has been introduced in the proposed design to reduce the readout time. This study also concerns about the effect of transistor sizing, bias current, and moreover, the chiral vector of CNTFET. The power consumption and power delay product (PDP) are also investigated for specific sets of reset and row selector signal. Data for these studies were collected with the help of HSPICE software which were further plotted in OriginPro to analyze the optimal operation point of APS circuit. The bias current was also recorded for the readout transistor which is uniquely introduced in the proposed model for achieving better readout time. Hence, the main focus of this paper is to improve the frame rate by reducing the readout time. Results of the proposed CNTFET APS circuit are compared with the conventional CMOS APS circuit. The performance benchmarking shows that CNTFET APS cell significantly reduces readout time, PDP, and thus can achieve much higher frame rate than that of conventional CMOS APS cell.
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