This paper presents a new SOI BCD technology at the 0.18 m node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25m .mm 2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability. Depletion NMOS, LV&HV diodes, 5V zener diode, high gain BJT, excellent matching well resistor, capacitors, top thick Copper Metallization option, embedded memory (OTP, CEEPROM, etc.) are also offered on this comprehensive technology platform.
the effect of recovery on Negative Bias Temperature Instability (NBTI) measurements had always been a challenge for reliability lifetime estimations. Currently various methods had been developed to suppress this characteristic but being able to completely remove it had been to no avail. This paper will first demonstrate the degree of impact of recovery on NBTI measurements; and then moving on to the influence of measurement system as well as testing time on NBTI lifetime estimation.
Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.
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