Emerging nonvolatile memories (ENVMs) such as phase-change random access memories (PCRAMs) or oxide-based resistive random access memories (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for field-programmable gate arrays (FPGAs) using ENVMs. We propose an ENVM-based configuration point, a look-up table structure with reduced programming complexity and a highperformance switchbox arrangement. We show that these blocks yield an improvement in area and write time of up to 3× and 33×, respectively, versus a regular Flash implementation. By integrating the designed blocks in an FPGA, we demonstrate an area and delay reduction of up to 28% and 34%, respectively, on a set of benchmark circuits. These reductions are due to the ENVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO 2 /Pt stack, while the lowest leakage power is achieved by InGeTe stack.Index Terms-3-D integration, nonvolatile memory, oxide memory, phase-change memory, programmable logic arrays, RRAM.
Abstract-Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals.
With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.
Abstract-Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of being monolithically integrated with CMOS chips, Resistive Random Access Memories (RRAMs) enable highperformance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs as well as the improved tolerance to power supply reduction, RRAM-based routing multiplexers can be used to significantly reduce the power consumption of FPGA systems with no performance compromises. By evaluating the opportunities of ultra-low-power RRAM-based FPGAs at the system level, we see an improvement of 12%, 26% and 81% in area, delay and power consumption at a mature technology node.
For over four decades, the semiconductor industry has experienced exponential growth. According to the International Technology Roadmap for Semiconductors, as we advance deeper into the era of nanotechnology, traditional Complementary Metal Oxide Semiconductor electronics will soon reach its physical and economical limits. This book deals with the opportunities offered by disruptive technologies and in particular explores novel designs for digital architectures (with an emphasis on reconfigurable structures).In a first approach, we will base our investigations around conventional FPGA architectures, and examine ways in which disruptive technologies can lead to structural improvements. In a more prospective approach, we will then also present some novel architectural schemes for ultra-fine grain computing, where the inherent properties of the considered disruptive technologies lead to reduced size of the logic elements.All these improvements are explored in a unified way by a new methodological approach, which allows the fast evaluation of an emerging technology on a prospective architecture. We use this to discuss their impact, from the level of simple circuits to that of complex architectures.Several technologies, ranging from 3D integration of devices (Phase Change Memories, Monolithic 3D, Vertical NanoWire-based transistors) to dense 2D arrangements (Double-Gate Carbon Nanotubes, Sublithographic Nanowires, Lithographic Crossbar arrangements), have been envisaged. Novel architectural organizations, as well as the associated tools, are presented in order to explore this largely uncharted design space.This book represents a new step in the field of nanoarchitectures. It makes the link between technology and applications by proposing prospective designs and toolflows adapted to the requirements of both sides. It thus lends precious insight into the field of emerging technologies for designers as well as technologists. Indeed, this book considers disruptive technologies from an architectural perspective, while all technological assumptions are validated. Thus, this book covers a broad range of fields that must be addressed holistically in such prospective research. v
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