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SUMMARYThe paper presents an algorithmic approach to a low-sensitivity design strategy for analog filter pairs based on a gyrator-capacitor prototype circuit. The general structure of the prototype circuit is proposed. It assumed that the generic structure of the prototype circuit can evolve, with the use of additional gyrators, into a circuit with increased redundancy. It is shown that symbolic analysis of the prototype circuit, used to formulate a set of nonlinear algebraic equations, is necessary to achieve a sufficiently high algorithm operation speed. To find a solution to this specific system of nonlinear algebraic equations, different numerical methods are compared. The modified Hooke and Jeeves algorithm is found to be the most effective. The elaborated algorithms and programs are illustrated with the seventh-order filter pair example. The obtained filter is better than the filter obtained using LC ladder structures with respect to chip area and power consumption, and these improvements are obtained without loss of sensitivity properties.

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SUMMARYThis paper presents an approach to a low-sensitivity design strategy for switched-current (SI) filter pairs based on a gyrator-capacitor prototype circuit. On the basis of a prototype filter, an SI counterpart circuit is obtained. Tools for SI filter design automation have been developed, which make a hardware description language -analog-mixed signal synthesization for the chosen kind of circuit. The obtained SI filter is better than the filter obtained using LC ladder structures with respect to very-large-scale integration complementary metal-oxide-semiconductor chip area and power consumption.

The aim of this paper is to show how the Hodgkin-Huxley model of the neuron's membrane potential can be extended to a stochastic one. This extension can be done either by adding fluctuations to the equations of the model or by using Markov kinetic schemes' formalism. We are presenting a new extension of the model. This modification simplifies computational complexity of the neuron model especially when considering a hardware implementation. The hardware implementation of the extended model as a system on a chip using a field-programmable gate array (FPGA) is demonstrated in this paper. The results confirm the reliability of the extended model presented here.

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