Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

Handkiewicz, Andrzej; Katarzyński, Piotr; Szczęsny, Szymon; Wencel, J.; Śniatała, Pawel

doi:10.1002/cta.741

Cited by 12 publications

(13 citation statements)

References 24 publications

(32 reference statements)

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“…From a system level viewpoint, there are several general methods available for generation and design of G m -C filters, including cascading of first and second-order sections, LC ladder simulationsubstituting passive inductances by gyrators-and multiple loop feedback [4,[21][22][23][24]. Besides, some techniques at topological level have been proposed in order to optimize the performance of classic fully differential G m -C topologies in terms of linearity, area, or power consumption.…”

Section: Design Techniques At System Levelmentioning

confidence: 99%

“…Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. ">Design techniques at system levelFrom a system level viewpoint, there are several general methods available for generation and design of G m -C filters, including cascading of first and second-order sections, LC ladder simulationsubstituting passive inductances by gyrators-and multiple loop feedback [4,[21][22][23][24]. Thus, two low-power second-order Butterworth G m -C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method.…”

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confidence: 99%

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Balanced G_m‐C filters with improved linearity and power efficiency

Algueta-Miguel

Blas

Lopez-Martin

2014

Circuit Theory & Apps

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A novel G m -C filter design technique is presented. It is based on floating-gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G m -C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all-pole G m -C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low-power second-order Butterworth G m -C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5-μm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. open-loop operation and the use of simpler topologies. However, these benefits come with the difficulty of achieving high linearity [4].Besides, the growing density of integration in CMOS technologies is reducing the thickness of the gate oxide of transistors, so supply voltages are also decreasing for reliability reasons: Voltages of 0.9 V are employed in modern technologies such as 90 nm and 65 nm, and the tendency is to keep decreasing. Furthermore, the growing proliferation of wireless and portable devices is leading to an intensive research on low-power integrated circuits for extending the lifetime of batteries.Thus, two challenging tasks are associated to G m -C filter design: linearity improvement to satisfy the modern communication standards and adaptation to the current low-voltage low-power requirements. Aimed to these goals, a novel G m -C filter design technique based on floating-gate MOS (FGMOS) transistors is proposed in this paper. It consists in a topological rearrangement of conventional filters without modifying the transconductor implementation and allows improving the filter linearity and relaxing the trade-off between the power consumption and the input range of the operational transconductance amplifier (OTA).The paper is organized as follows. In Section 2, an overview of several G m -C filter design methods available in the technical literature is presented. In Section 3, the fundamentals of the proposed FGMOS technique are explained, and considerations for applying it to G m -C filter design are discussed. The second-order effects of the presented method are studied in Section 4. In Section 5, a conventional second-order Butterworth G m -C filter is compared with its equivalent implementation obtained using the proposed design technique. Finally, conclusions are drawn in Section 6. All the proposed circuits have been fabrica...

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Section: Design Techniques At System Levelmentioning

confidence: 99%

mentioning

confidence: 99%

Balanced G_m‐C filters with improved linearity and power efficiency

Algueta-Miguel

Blas

Lopez-Martin

2014

Circuit Theory & Apps

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“…Parameters of the gyrator-capacitor prototype were calculated using the method proposed in [15]. Choosing the calculation method depends on hardware resources of the FPAA matrix, especially concerning the size of the grid calculated for the RCM circuit.…”

Section: Elliptic Filtermentioning

confidence: 99%

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR = 40.42 dB, 2D-DCT processor with PSNR = 53.05 dB and RGB-to-YCrCb converter with PSNR = 46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

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“…The proposed SI-Studio environment allows to obtain the final topography of an SI circuit chip in a case of a gyrator-capacitor prototype circuit (methods for obtaining automatically such a circuit were previously published in [4,5]) or in a case of a switched-current prototype network without a given transistor level description. SI-Studio is in fact an environment of integrated applications realising subsequent design steps.…”

Section: Assumptions and Conceptsmentioning

confidence: 99%

SI-Studio – environment for SI circuits design automation

Szczęsny¹,

Naumowicz²,

Handkiewicz³

2012

Bulletin of the Polish Academy of Sciences: Technical Sciences

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Abstract. The current work is an answer to the problem of designing switched-current (SI) circuits, which is usually a complex issue in the field of microelectronics. The mentioned task is a source of many mistakes and takes a lot of time for designers, therefore authors of the article decided to propose a software solution. This article presents an environment for design automation of analogue circuits in the switched currents technique. It points out the utility advantages of the described tools, which make the work of a VLSI designer much easier, moreover offering a possibility to parameterise the design process considering power consumption, chip area usage and its working speed. It also presents results of an automatic generation of a filter pair circuit, as well as a DCT circuit -automatically generated with the proposed SI-Studio software tools.

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Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

Cited by 12 publications

References 24 publications

Balanced G_m‐C filters with improved linearity and power efficiency

Balanced G_m‐C filters with improved linearity and power efficiency

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SI-Studio – environment for SI circuits design automation

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Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

Cited by 12 publications

References 24 publications

Balanced Gm‐C filters with improved linearity and power efficiency

Balanced Gm‐C filters with improved linearity and power efficiency

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SI-Studio – environment for SI circuits design automation

Contact Info

Product

Resources

About

Balanced G_m‐C filters with improved linearity and power efficiency

Balanced G_m‐C filters with improved linearity and power efficiency