The large particle count ͑LPC͒ of fumed silica slurries was evaluated and correlated with scratch counts created on SiO 2 films by table-top, chemical-mechanical planarization ͑CMP͒. Particle sizing results obtained by static light scattering, capillary hydrodynamic fractionation, and dual-sensor single particle optical sensing ͑SPOS͒ pointed to the latter as the superior method for quantitative analyses of the LPC. Dual-sensor SPOS is a new technique that determines the LPC on a silica sphere-equivalent, light-scattering diameter scale for particles as small as 0.469 m. LPC measurements used in combination with dark-field optical microscopy for scratch metrology afforded linear correlations between scratch counts and the LPC. Particles producing scratches had silica sphere-equivalent, light-scattering diameters exceeding 0.68 m. Inclusion of these particles in the LPC produced a two-fold increase in the number of scratch-forming particles in the correlation relative to correlations generated via single-sensor SPOS measurements of LPC. Experimental uncertainty in scratch counts limited the correlation as a scratch predictor. Slurries differing in LPC by a minimum of 1.8 ϫ 10 5 particles/g slurry had statistically different predicted scratch counts at the 95% confidence level. Additional method development is needed to extend LPC-based scratch prediction to other CMP processes producing scratch defects.Among the set of key criteria defining the limits of microelectronic device fabrication, the reduction of surface defects assumes special prominence. It is well established 1 that surface defects on a microelectronic device degrade device performance. A variety of defect types, including delaminated film interfaces, pits, scratches, and chemical and physical changes in film structures, have been identified as the products of surface-damaging events during device fabrication. 1 Given the overwhelming need to reduce the size of microelectronic devices in order to produce faster and more powerful commercial microprocessors, strategies for reducing all types of surface defects have become a critical element of the fabrication processes used by the microelectronic device industry.Reaching the desired state of minimized surface defects on microelectronic devices begins with the recognition that a principal source of surface defects in device fabrication processes is surface polishing and planarization afforded by chemical-mechanical planarization ͑CMP͒. 2,3 The current paradigm of CMP-driven defect generation attributes the creation of defects to the mechanical action of the largest diameter particles in a CMP slurry. 4-6 Although a detailed mechanistic understanding of this process remains elusive, research efforts have sparked the development of many new analytical methods and techniques for the characterization of the abrasive particles and other consumables in CMP slurries. 7 A key analytical metric, widely applied to predict the defect creation potential of CMP slurries, is the large particle count ͑LPC͒ for the slur...
This work reviews the mechanical properties and fracture mechanics of materials important in the manufacture of multilayer interconnects on silicon chips in order to understand surface damage caused during chemical mechanical polishing (CMP). It 2 gives an explanation for chatter marks, surface flaking in interlayer dielectric material (ILD) and rolling indenter and plastic plow lines in copper on the wafer surface during CMP of silicon chips.
In order to enable high-k metal gate technology, new CMP steps and slurries are needed to meet the stringent planarity and defect requirements for device performance. This paper will describe several of these slurry technologies in detail, including poly-openpolish, Aluminum CMP, and improvements required in Tungsten polishing. The keys to these technologies are outlined and polishing performance given in detail. The critical mechanisms involved in the material polishing for each of these steps are also introduced. All of these new technologies are needed in order to build a successful high-k metal gate device for advanced node integration via a replacement gate build strategy.
The British retail banking market has changed markedly since the beginning of the 1970s, and important trends and developments have increased the competitive pressures facing banks. The whole nature of competition in British retail banking has altered. New competitors and new forms of competition have appeared with increasing rapidity. These changes and the associated pressures on banks have intensified during the 1980s. At the same time, banks have increased the comparative importance of retail banking within their strategies. These pressures and their associated implications for British retail banking strategy are explored. It is emphasised that marketing will need increasingly to dominate bank strategies in retail banking. This orientation towards marketing has important strategic and managerial consequences for banks.
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