Cardiovascular risk factors in people on antiretroviral treatment (ART) are poorly documented in resource-constrained settings. A cross-sectional study was conducted in 2009 to assess prevalence of diabetes and hypertension in a sample of 242 HIV-infected patients who had initiated ART between 1998 and 2002 in Dakar, Senegal (ANRS 1215 observational cohort). World Health Organization (WHO) criteria were applied to diagnose diabetes and hypertension. Multiple logistic regressions were used to identify factors associated with diabetes and hypertension. Patients had a median age of 46 years and had received ART for a median duration of about 9 years. 14.5% had diabetes and 28.1% had hypertension. Long duration of ART (≥119 months), older age, higher body mass index (BMI), and higher levels of total cholesterol were associated with higher risks of diabetes. Older age, higher BMI at ART initiation, and higher levels of triglycerides were associated with higher risk of hypertension. This study shows that diabetes and hypertension were frequent in these Senegalese HIV patients on ART. It confirms the association between duration of ART and diabetes and highlights the need to implement programs for prevention of cardiovascular risk factors in HIV patients from resource-constrained settings.
Hardware Trojans (HTs) are malicious alterations to a circuit. These modifications can be inserted either during the design phase or during the fabrication process. Due to the diversity of Hardware Trojans, detecting and/or locating them are challenging tasks. Numerous approaches have been proposed to address this problem. Methods based on logic testing consist in trying to activate potential HTs and detect erroneous outputs during test. However, HTs are stealthy in nature i.e. mostly inactive unless they are triggered by a very rare condition. The activation of a HT is therefore a major challenge. In this paper, we propose a new testing procedure dedicated to identifying where a possible HT may be easily inserted and generating the test patterns that are able to excite these sites. The selection of the sites is based on the assumption that the HT (i) is triggered by signals with low controllability, (ii) combines them using gates in close proximity in the circuit's layout, and (iii) without introducing new gates in critical paths.
The insertion of malicious alterations to a circuit, referred to as Hardware Trojans, is a threat considered more and more seriously during the last years. Numerous methods have been proposed in the literature to detect the presence of such alterations. More recently, Design-for-Hardware-Trust (DfHT) methods have been proposed, that enhance the design of the circuit in order to incorporate features that can either prevent the insertion of a HT or that can help detection methods. This paper focuses on a HT prevention technique that aims at creating a layout without filler cells, which are assumed to provide a great opportunity for HT insertion, in order to make the insertion of a HT in a layout as difficult as possible.
Hardware Trojans (HTs) are ultimately a dangerous threat in semiconductor industry. The serious impact of HTs in security applications and global economy brings extreme importance to their detection and prevention techniques. This paper focuses on developing a HT prevention techniques through a layout level design approach. The principle is to let no available space on silicon for an attacker to insert a HT. Experiments determine the maximum occupational rate and critical empty spaces while filling with standard cells. The proposed technique makes HT insertion nearly impossible.
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