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AbstractThe objective of this paper is to generate a ApplicationOriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-
redundant fault'. Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattem generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattem generation petformed on a FPGArepresentation is required. it is then demonstrated that test pattem generation performed on the FPGA representation can be significantly accelerated by removing' most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.
The objective of this paper is to generate an Application-Oriented Test Procedure to be used b y a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault'. Then, it is commented that a classical test pattern generation performed on the circuit rietlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation perfornled on a FPGA representation is required. It is also conznzented that test pattern generation performed on the FPGA representation can be signqicantlp accelerated b y different techniques. A procedure called TOF is described to validate the proposed upproach on benchmark circuits.
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