This paper presents aligned carbon nanotube (CNT) synaptic transistors for large-scale neuromorphic computing systems. The synaptic behavior of these devices is achieved via charge-trapping effects, commonly observed in carbon-based nanoelectronics. In this work, charge trapping in the high- k dielectric layer of top-gated CNT field-effect transistors (FETs) enables the gradual analog programmability of the CNT channel conductance with a large dynamic range ( i. e., large on/off ratio). Aligned CNT synaptic devices present significant improvements over conventional memristor technologies ( e. g., RRAM), which suffer from abrupt transitions in the conductance modulation and/or a small dynamic range. Here, we demonstrate exceptional uniformity of aligned CNT FET synaptic behavior, as well as significant robustness and nonvolatility via pulsed experiments, establishing their suitability for neural network implementations. Additionally, this technology is based on a wafer-level technique for constructing highly aligned arrays of CNTs with high semiconducting purity and is fully CMOS compatible, ensuring the practicality of large-scale CNT+CMOS neuromorphic systems. We also demonstrate fine-tunability of the aligned CNT synaptic behavior and discuss its application to adaptive online learning schemes and to homeostatic regulation of artificial neuron firing rates. We simulate the implementation of unsupervised learning for pattern recognition using a spike-timing-dependent-plasticity scheme, indicate system-level performance (as indicated by the recognition accuracy), and demonstrate improvements in the learning rate resulting from tuning the synaptic characteristics of aligned CNT devices.

Single and double pulse doped metamorphic high electron mobility transistor (MHEMT) structures have been grown on GaAs substrates by molecular beam epitaxy. A linear indium graded buffer layer was used to expand the lattice constant. Transmission electron microscopy cross sections showed planar interfaces. Threading dislocations were not observed along both cleavage directions. For a single pulse doped MHEMT structure with an In0.56Ga0.44As channel layer, the mobilities (10 030 cm2/V s at 292 K; 32 560 cm2/V s at 77 K) and sheet density (3.2×1012 cm−2) were nearly equivalent to values obtained for the same structure grown on an InP substrate. Secondary ion mass spectroscopy measurements of a double pulse doped structure indicated no measurable migration of the silicon doping pulses. MHEMT devices with 0.15 μm gates were fabricated, tested, and compared to GaAs pseudomorphic HEMT devices of the same geometries. Above 9 GHz, the MHEMT devices exhibited lower noise figure. From 3 to 26 GHz, the associated gain was 3 dB higher with the MHEMT devices. Also higher linearity performance was obtained with the MHEMT devices. At 4 GHz MHEMT linearity measurements yielded third order intermodulation distortion intercepts, IP3, of 36–39 dBm with linearity figure of merits of 60–90. Due to the significantly lower cost and more robustness of GaAs substrates compared to InP substrates, MHEMT technology is very promising for low cost manufacturing of low noise amplifiers.

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RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.

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