No abstract

Modern system-on-chip designs contain multiple computational cores with several levels of caches, as well as a sophisticated memory subsystem. Functional verification of multi-core microprocessor models is known to be a big challenge. There are different approaches for memory subsystem and cache coherence controllers verification but an automated functional test generation strategy is the most commonly used in the industry. In this paper, the technique of automated multi-core test generation is proposed. It can be applied for cache coherence and memory subsystem check in a top-level multi-core RTLmodel simulation. Moreover, the presented test generator can be very effective in generating test scenarios for FPGAprototypes of SoC being designed. In this paper, we also give a detailed description of the random test generator itself and the capabilities of generated test cases. The proposed test generator got its name Ristretto due to the similarity of the word Ristretto with the abbreviation formed from the words "random instruction sequence" (RIS), and the word "threads" (and because ristretto is so concentrated and intense). Some self-checking validation approaches are suggested to obtain correct responses in FPGA-based verification (postsilicon validation). In the paper, we also discuss the bugmasking problem in post-silicon random instruction tests that arises due to limited observability.

No abstract

Atomic operations functional verification is known to be a rather labour-intensive process because atomic operations cannot be tested with the help of stochastic test generation methods due to their unpredictable nature. verification strategy and process to adjust to a new project design.