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Atomic operations functional verification is known to be a rather labour-intensive process because atomic operations cannot be tested with the help of stochastic test generation methods due to their unpredictable nature. verification strategy and process to adjust to a new project design.

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In the paper the early stage of verification technology for multicore processor models testing is proposed. We demonstrate the applicability of the single core verification method extension where creating new multicore test generator is not required. The solution scheme deals with the adaptation method of some available single core stochastic testing approaches to a fully functional multicore testing tool. The proposed technique has been successfully applied to test RTL model of dual-core microprocessor with SMP developed in SRISA. The discussed approach was initially considered to be the first stage of RTL model testing, but the possibilities of the approach are also of interest for testing the model at the later stages of its design and functional maturity. The testing process begins by creating simple random tests that check the MOESI coherence protocol. A new advanced random testing method based on the usage of proposed interleaved memory structures is developed to increase the probability of finding rare and hard to detect bugs in the memory subsystem. The great advantage of the proposed memory allocation structure is that both cores gain access to the same cache-line simultaneously for read and write. Despite this accessibility, the methodology avoids losses of data consistency due to cores access to different bytes. Furthermore, each common area that is allowed to write to more than one core will contain deterministic values at every time. The proposed approach aims to detect failures in cache coherence protocol, memory subsystem and memory buffers. Also, this testing system helps to find machine state errors that lead to deadlock.