Au overview of phase locking in two-dimensional (2D) arrays of identical Josephson junctions is presented. General design criteria are discussed for optimization of power and linewidth. A harmonic balance technique is used to derive an analytic expression for the fundamental power as a function of bias voltage for a single shunted tunnel junction with an external shunt resistor having parasitic inductance. A linear stability analysis is performed on the in-phase state of 2D arrays in the absence of any external load. Most excitation modes in the 2D array are damped, leading to stable phase locking between parallel junctions within each row; however, within the theoretical model, no mechanisms intrinsic to the array were found to induce phase locking between rows of junctions. The results of these calculations and their impact on and relevance to the design of phase-locked Josephson oscillators are discussed.

No abstract

We have coupled emission from 10×10 arrays of Josephson junctions at 4 K to a room-temperature mixer through a fin-line antenna and a WR-12 waveguide. A single voltage-tunable peak was detected in the frequency range from 53 to 230 GHz. A stripline resonance in the antenna reduced the array’s dynamic resistance and thereby the emission linewidth to as low as 10 kHz. We extract an effective noise temperature of 14 K from the linewidth data.

We have experimentally coupled emission from a distributed series array of 1968 wide Josephson junctions to an on-chip 10.8 Ω load and detected 0.16 mW at 240 GHz. This result is achieved by reducing the parasitic inductance associated with shunt resistors so that junctions with critical currents of 23 mA are effectively shunted at the operating frequency. This power is less than the 1.3 mW expected from theory due to the presence of a large impedance mismatch. Optimization of the load design will allow the detection of mW power.

A superconducting integrated circuit fabrication process has been developed to encompass a wide range of applications such as Josephson voltage standards, VLSI scale array oscillators, SQUIDS, and kinetic-inductance-based devices. An optimal Josephson junction process requires low temperature processing for all deposition and etching steps. This low temperature process involves an electron cyclotron resonance-based plasma-enhanced chemical vapor deposition of SiO, films for interlayer dielectrics. Experimental design and statistical process control techniques have been used to ensure high quality oxide films. Oxide and niobium etches include endpoint detection and controlled overetch of all 6lms. An overview of the fabrication process is presented.