Abstract-An algorithm for architecture-level exploration of the 16 A/D converter (ADC) design space is presented. Starting from the desired specification, the algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with a single-bit or multibit quantizer, for a range of oversampling ratios. A fast filter-level step evaluates the performance of all loop-filter topologies and passes the accepted solutions to the architecture-level optimization step which maps the filters on feasible architectures and evaluates their performance. The power consumption of each accepted architecture is estimated and the best top-ten solutions in terms of the ratio of peak signal-to-noise+distortion ratio versus power consumption are further optimized for yield. Experimental results for two different design targets are presented. They show that previously published solutions are among the best architectures for a given target but that better solutions can be designed as well.Index Terms-Analog-to-digital converter (ADC), analog-to-digital, computer-aided design (CAD), delta-sigma, design automation.
The design of a delta-sigma (16) analog-to-digital converter (ADC) for direct voltage readout of an electret microphone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged together with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourthorder 16 ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise+distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumentation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A combined continuous-time/switched-capacitor design is used to minimize power consumption.
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