A scanning surface potential measurement technique suited for thin-film devices operating under high voltages is reported. A commercial atomic force microscope has been customized to enable a feedback-controlled and secure surface potential measurement based on phase-shift detection under ambient conditions. Measurements of the local potential profile along the channel of bottom-gate organic thin-film transistors (TFTs) are shown to be useful to disentangle the contributions from the channel and contacts to the device performance. Intrinsic contact current-voltage characteristics have been measured on bottom-gate, top-contact (staggered) TFTs based on the small-molecule semiconductor dinaphtho[2,3-b:2 0 ,3-f]thieno[3,2-b]thiophene (DNTT) and on bottom-gate, bottomcontact (coplanar) TFTs based on the semiconducting polymer polytriarylamine (PTAA). Injection has been found to be linear in the staggered DNTT TFTs and nonlinear in the coplanar PTAA TFTs. In both types of TFT, the injection efficiency has been found to improve with increasing gate bias in the accumulation regime. Contact resistances as low as 130 X cm have been measured in the DNTT TFTs. A method that eliminates the influence of bias-stress-induced threshold-voltage shifts when measuring the local charge-carrier mobility in the channel is also introduced, and intrinsic channel mobilities of 1.5 cm 2 V À1 s À1 and 1.1 Â 10 À3 cm 2 V À1 s À1 have been determined for DNTT and PTAA. In both semiconductors, the mobility has been found to be constant with respect to the gate bias. Despite its simplicity, the Kelvin probe force microscopy method reported here provides robust and accurate surface potential measurements on thin-film devices under operation and thus paves the way towards more extensive studies of particular interest in emerging fields of solid-state electronics. V

It has been shown recently that the low voltage gate current in ultrathin oxide metal–oxide–semiconductor devices is very sensitive to electrical stresses. Therefore it can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements to be used. This paper presents a thorough study of the low voltage gate current variation for different uniformed or localized electrical stress conditions at or above room temperature, and for various oxide thicknesses ranging from 1.2 to 2.5 nm. As it has been proposed recently that this current could be due to electron tunneling through Si/SiO2 interface states, the results obtained in the thicker oxides for the gate current have been compared with the corresponding surface state density variations measured by charge pumping. It is shown that there is no clear relation between low voltage gate current increase after stress and that of surface state density, and that soft or hard oxide breakdown happens when the low voltage current reaches a critical value independently of the stress created interface state density.

Current-voltage and Kelvin probe force microscopy (KPFM) measurements were performed on single ZnO nanowires. Measurements are shown to be strongly correlated with the contact behavior, either Ohmic or diode-like. The ZnO nanowires were obtained by metallo-organic chemical vapor deposition (MOCVD) and contacted using electronic-beam lithography. Depending on the contact geometry, good quality Ohmic contacts (linear I-V behavior) or non-linear (diode-like) contacts were obtained. Current-voltage and KPFM measurements on both types of contacted ZnO nanowires were performed in order to investigate their behavior. A clear correlation could be established between the I-V curve, the electrical potential profile along the device and the nanowire geometry. Some arguments supporting this behavior are given based on technological issues and on depletion region extension. This work will help to better understand the electrical behavior of Ohmic contacts on single ZnO nanowires, for future applications in nanoscale field-effect transistors and nano-photodetectors.

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An improved setup for accurate near-field surface potential measurements and characterisation of biased electronic devices using the Kelvin Probe method has been developed. Using an external voltage source synchronised with the raster-scan of the KPFM-AM, this setup allows to avoid potential measurement errors of the conventional Kelvin Probe Force Microscopy in the case of in situ measurements on biased electronic devices. This improved KPFM-AM setup has been tested on silicon-based devices and organic semiconductor-based devices such as organic field effect transistors (OFETs), showing differences up to 25% compared to the standard KPFM-AM lift-mode measurement method.