This paper presents the implementation of a new topology of 3D slow-wave transmission lines in CMOS technology.The proposed structure makes it possible to consider the design of compact circuits based on these 3D transmission lines presenting performances superior to the lumped elements approach (inductors and capacitors) for the Ka band, and in particular for 5G applications. The equivalent electrical model of the 3D structure, based on a physical analysis, is established, with excellent agreement with the measurement results. Then a filter based on parallel stubs is proposed in order to show the potentialities of the proposed 3D structure. The performances obtained are acceptable, with a power balance showing insertion loss potentially equal to 3 dB if the structure is matched, for a relative bandwidth of 22%. Development prospects concern the design of more complex filters but also of matching networks for LNAs or PAs.
This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50-Ω load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50-Ω load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50-Ω load connection.
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