Abstract-This paper presents a match-line (ML) sensing scheme that distinguishes a match from a miss by first shunting every ML with a fixed negative resistance, then exciting the MLs with an initial charge, and subsequently observing their voltage developments. It is shown that the voltage on the matched ML will grow to V DD , as in an unstable system, whereas the voltage on a missed ML will decay to zero, as in a stable system. Since the initial excitation charge on the ML's can be as low as the noise level in the system, this scheme can approach the minimum possible energy consumption level for match-line sensing.We have implemented, in 0.18 m CMOS, a 144 144 ternary CAM array that includes the stability-based sensing scheme along with two previously-reported sensing schemes. The measured results confirm the power savings of the proposed sensing scheme. In addition, the CAM includes a pipelined search-line (SL) architecture that can reduce the SL portion of CAM power by up to 50%.Index Terms-Content-addressable memory, CAM, stability-based sensing, match-line sensing, match-line power, search-line pipelining, search-line driving, search-line power.
Abstract-This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully confirmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies 0.51 mm 2 , and consumes 178.4 mW at 5 Gb/s.Index Terms-Clock and data recovery, CDR, ADC-based CDR, feed-forward CDR, blind-sampling CDR, all-digital CDR.
A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSCmodulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to -5000ppm.The transceiver consists of three blocks, a clock generator, a transmitter and a receiver (Fig. 8.7.1). The clock generator uses a 4-phase 2.5-GHz SSC-compliant PLL. The resulting 4-phase 2.5-GHz clock is distributed to the transmitter and the receiver. The transmitter performs 16-to-1 multiplexing to generate the 5-Gb/s serial data from the 312.5-MHz 16-bit parallel data. The output driver has a 2-tap FIR filter, achieving a nominal de-emphasis level of 3.5dB.The receiver analog front-end is a continuous-time analog equalizer followed by a 4-way interleaved 10-GS/s flash 5-bit ADC (Fig. 8.7.1). The analog equalizer gives a nominal gain boost of 6 dB at 2.5 GHz to the incoming signal by using an RC-degenerated differential pair. The ADC converts the equalizer output into 5-bit data stream at 10GS/s or 2 times per UI. The binary data are then demultiplexed into 625-Mb/s 16-parallel 5-bit words and transferred to the digital backend block. The digital back-end block further equalizes the signal by using an FFE, which is a half-UI-spaced 2-tap FIR filter. The filter tap coefficients are controlled adaptively by a control logic implemented in the digital back-end. After the analog and digital equalization, the signal is sent to a digital CDR that operates at 625MHz.The digital CDR tracks the center of the data eye and makes binary decision by slicing the data at the eye center. Unlike the conventional phase-tracking CDRs, the phase tracking and the data slicing are done entirely in the numerical domain (Fig. 8.7.2). The CDR first extracts the data's zero-crossing timing, or the instantaneous phase, ph i , by using a linear interpolation. The instantaneous phase represents where in a one-UI period the zero crossing happens, and is expressed in a three-bit code. An averaged version of the instantaneous phase, ph av , is generated by using a second-order filter that consists of a modulo-1UI error subtractor followed by two integrators. The eye-center phase is est...
ADC-based CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sample the signal at 1× or 2× the baud rate. The 1× CDR aligns the sampling clock with the signal using a phase-tracking feedback loop [1][2], which requires a voltage-controlled oscillator or phase interpolator, both analog circuits, to adjust the phase of the sampling clock. To eliminate these analog circuits (and their phase control) in favor of an all-digital implementation, a blind-sampling ADC-based CDR (top of Fig. 8.6.1) samples the received signal at 2× without phase locking to the signal. The CDR then interpolates between the blind samples to obtain a new set of samples in order to recover the phase and data [3][4]. The doubling of the sampling rate, however, increases the ADC power consumption or, equivalently, reduces the maximum baud rate due to the conversion-rate limitations of ADCs. This paper presents a new fractional-sampling-rate (FSR) CDR architecture, shown in Fig. 8.6.1, that samples the received signal blindly at a fractional rate of 1.45×, hence reducing the ADC power per Gb/s of data rate by 27.3% compared to the 2× architecture. This architecture uses a digital phase detector (PD) that estimates the data phase directly from the blind digital samples, thus eliminating the need for interpolation. This PD enables data recovery in a feed-forward path, further simplifying the CDR architecture. Measurements of a test-chip fabricated in 65nm CMOS confirm that the FSR CDR successfully recovers data with BER<10 -13 at 6.875Gb/s from samples taken at 10GS/s.A block-diagram of the CDR architecture is shown in Fig. 8.6.2. We blindly sample a 6.875Gb/s signal with four time-interleaved 2.5GS/s 5-bit flash ADCs for a total sampling rate of 10GS/s, corresponding to 1.45 samples per unit interval (UI). This sampling rate makes the sampling interval (SI) equal to 11/16 UIs, which causes the sampling instances to span the full duration of a UI. A 4:16 DeMUX then feeds 16 samples at a time, corresponding to 11 UIs, to the digital CDR. The PD estimates the instantaneous zero-crossing phase, φ X [1:16], for every UI, using a scheme we describe later. We use φ X to recover the average zero-crossing phase, φ AVG , in two steps. First, the phase subtractor generates the phase error, φ ERR , with a modulo-subtraction of φ AVG from φ X , bounding φ ERR within [-0.5; 0.5) UI. Then, φ ERR is fed into a third-order low-pass filter to recover φ AVG . The filter consists of three discrete-time integrators with programmable gains, K 1 , K 2 , and K 3 , that control the CDR's jitter-tracking bandwidth. The data decision block picks one sliced sample per UI as the recovered data by comparing φ X [n] and φ AVG , and marks duplicate samples, present in some UIs due to the FSR, as invalid samples. We remove these invalid samples from the data-decision vector, Ŝ[1:16], with a vector compactor (described...
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