A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

Abstract

A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSCmodulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to -5000ppm.The transceiver consists of three blocks, a clock generator, a transmitter and a receiver (Fig. 8.7.1). The clock generator uses a 4-phase 2.5-GHz SSC-compliant PLL. The resulting 4-phase 2.5-GHz clock is distributed to the transmitter and the receiver. The transmitter performs 16-to-1 multiplexing to generate the 5-Gb/s serial data from the 312.5-MHz 16-bit parallel data. The output driver has a 2-tap FIR filter, achieving a nominal de-emphasis level of 3.5dB.The receiver analog front-end is a continuous-time analog equalizer followed by a 4-way interleaved 10-GS/s flash 5-bit ADC (Fig. 8.7.1). The analog equalizer gives a nominal gain boost of 6 dB at 2.5 GHz to the incoming signal by using an RC-degenerated differential pair. The ADC converts the equalizer output into 5-bit data stream at 10GS/s or 2 times per UI. The binary data are then demultiplexed into 625-Mb/s 16-parallel 5-bit words and transferred to the digital backend block. The digital back-end block further equalizes the signal by using an FFE, which is a half-UI-spaced 2-tap FIR filter. The filter tap coefficients are controlled adaptively by a control logic implemented in the digital back-end. After the analog and digital equalization, the signal is sent to a digital CDR that operates at 625MHz.The digital CDR tracks the center of the data eye and makes binary decision by slicing the data at the eye center. Unlike the conventional phase-tracking CDRs, the phase tracking and the data slicing are done entirely in the numerical domain (Fig. 8.7.2). The CDR first extracts the data's zero-crossing timing, or the instantaneous phase, ph i , by using a linear interpolation. The instantaneous phase represents where in a one-UI period the zero crossing happens, and is expressed in a three-bit code. An averaged version of the instantaneous phase, ph av , is generated by using a second-order filter that consists of a modulo-1UI error subtractor followed by two integrators. The eye-center phase is est...

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS

“…However, for typical channels with higher attenuation, a 2-tap DFE or a combination of the 1-tap DFE with a linear equalizer should be used. Theoretically the DFE combined with the FFE presented in [5] is capable of equalizing channels up to 28 dB. Fig.…”

“…This extra equalization can be done either as a feed-forward equalizer (FFE) or a decision-feedback equalizer (DFE). An FFE [5] boosts both the signal and the noise at high frequencies. This noise, in the case of ADC-based CDR, includes the ADC quantization noise that may limit the performance.…”

“…We explain the details of the ADC design [5], the feed-forward CDR [4], and the DFE as it was presented in [6] in the background section. The details of the proposed adaptive DFE will be discussed in Section III, followed by simulation and measurement results in Section IV and conclusions in Section V.…”

A 5Gb/s speculative DFE for 2x blind ADC-based receivers in 65-nm CMOS

“…In a phase-tracking RX, the DFE relies on the recovered clock from the incoming signal for its operation [2]. In a blind ADC-based RX, however, there is no recovered clock [1]; the sampling clock is totally blind. This makes the task of DFE design nontrivial as the samples of the incoming signal no longer correspond to the centre of the eye or to any specific data phase.…”

“…3 depicts the full-rate implementation of the proposed RX in a simplified block diagram. Two ADC samples of the current UI, S [1:2] , along with one delayed sample of the previous UI, S 0 , form the 3 consecutive samples, S [0:2] , needed by the CDR to recover b n [1]. The DFE Coefficient Selector (DCS) uses the current value of Φ AVG to select the two coefficients, c [1:2] , which correspond to the location of S [1:2] from α [0:7] .…”