This work presents the influence of Thin Wafer und Laser Anneal Technology on the electrical performance of 4HSiC devices. Substrate thinning and backside ohmic contact formation via laser annealing were successfully applied to in-house designed and manufactured 6 A 650 V SiC diodes at IISB, improving its forward characteristics. The given devices exhibit an on-state voltage drop (VF) reduction from 1.78 V to 1.62 V at 6 A rated current while maintaining blocking capabilities of more than 1.1 kV with leakage currents less than 1 μA at 650 V nominal voltage. On-resistance (RON) was lowered by approx. 30 % to 90 mΩ and 60 % to 12 mΩ in Schottky and conductivity modulation state, respectively. Wafer thinning also allows reducing the influence of non-homogeneous distributed substrate doping concentrations, leading to a more narrow distribution of the forward characteristics of the devices across the wafer.
In this work, pulsed-laser-based tempering was applied for post-implant annealing of n-type N-doped 4H-SiC in order to electrically activate the dopants and to rebuild the crystal structure. The annealing was performed by a frequency-tripled Nd:YVO4 laser with a pulse duration of 60 ns. To evaluate the effects of post-implant annealing, JBS diodes were electrically characterized. The results were compared with implanted, not post-annealed JBS diodes. The electrical measurements showed a significant on-state voltage drop of 40 mV at 6 A for post-implant laser annealed diodes compared to not post-implant annealed diodes.
A systematic experimental study is conducted on floating field rings (FFR) incorporated into 4H-SiC junction barrier Schottky (JBS) diodes across four voltage ratings 650, 1200, 1700 and 3300V, in pursuit of highly efficient FFR designs. 30 designs of FFR in 3 categories are studied for each voltage rating, and the measured breakdown voltage (Vbr) of JBS divided by ring system width (W) is taken as the figure of merit (FOM) of each design. The influence of ring spacing, ring width and number of rings on Vbr is studied in detail. It is found that the initial ring spacing (S1) is critical in determining the highest Vbr achievable by a certain design, and its optimum value increases as voltage rating increases. TCAD simulation verifies the importance of S1. For designs with a small ring system width, subsequent ring spacing can also become important. Ring width does not have a definitive effect, and Vbr saturates beyond a certain ring number. The design with the highest Vbr may not render the highest FOM. Even style designs with appropriate ring spacings can be advantageous likely due to less susceptibility to variation of field oxide charge, and more tolerance to fabrication error, as well as ease of design.
This work presents a design study of customized p+ arrays having influence on the electrical properties of manufactured 4H-SiC Junction Barrier Schottky (JBS) diodes with designated electrical characteristics of 5 A forward and 650 V blocking capabilities. The effect of the Schottky area consuming p+ grid on the forward voltage drop, the leakage current and therefore the breakdown voltage was investigated. A recessed p+ implantation, realized through trench etching before implanting the bottom of the trenches, results in a more effective shielding of the electrical field at the Schottky interface and therefore reduces the leakage current. Customizing the p+ grid array in combination with the trench structure, various JBS diode variants with active areas of 1.69 mm2 were fabricated whereas forward voltage drops of 1.58 V @ 5 A with blocking capabilities up to 1 kV were achieved.
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