An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mmx6.8 mm in a 2.0 mum scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented.
A trainable VLSI neuroprocessor for adaptive vector quantization based upon the frequency-sensitive competitive learning algorithm has been developed for high-speed high-ratio image compression applications. Simulation results show that such an algorithm is capable of producing goodquality reconstructed image at high compression ratios of more than 20. This neural network-based vector quantization design includes a fully parallel vector quantizer and a pipelined codebook generator which obtains a time complexity O(1) for each quantization vector.A 5x5-dimentional vector quantizer prototype chip has been designed, fabricated and tested. It contains 64 inner-product neural units and an extendable winner-take-all block. This mixed-signal chip occupies a compact silicon area of 4.6 x 6.8 mm2 in a 2.0-pm scalable CMOS technology. It provides a computing capability as high as 3.33 billion connections per second. It can achieve a speedup factor of 750 compared with a SUN-3/60 for a compression ratio of 33. Real-time adaptive VQ on industrial 1,024 x 1,024 pixel images is feasible using an extended array of such neuroprocessor chips. An industrial-scale chip of 125 mm2 size to achieve 104 billion connections per second for the 1024-codevector vector quantizer can be fabricated in a I-pm CMOS technology.
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