Matrix multiplication is the kernel operation used in many transform, image and discrete signal processing application. We develop new algorithms and new techniques for matrix multiplication on configurable devices. In this paper, we have proposed three designs for matrix-matrix multiplication. These design reduced hardware complexity, throughput rate and different input/output data format to match different application needs. These techniques have been designed implementation on Virtex-4 FPGA. We have synthesized the proposed designs and the existing design using Synopsys tools. Interestingly, the proposed parallel-fixed-input and multiple-output (PPI-MO) structure consumes 40% less energy than other two proposed structures and 70% less energy than the existing structure.
We known that different multipliers consume most of the power in DSP computations, FIR filters. Hence, it is very important factor for modern DSP systems to built low-power multipliers to minimize the power dissipation. In this paper, we presents high speed & low power Row Column bypass multiplier design methodology that inserts more number of zeros in the multiplicand thereby bypass the number of zero in row & Column as well as reduce power consumption. The bypassing of zero activity of the component used in the process of multiplication, depends on the input bit data. This means if the input bit data is zero, corresponding row and column of adders need not be addition & transfer bit in next row and column adder circuit. If multiplicand having more zeros, higher power reduction can be achieved. At last stage of Row & column bypass multiplier having ripple carry adder which are increase time to generate carry bit to transfer next adder circuit. To reduce this problem by using Carry bypass adder in place of ripple carry adder, then new modification of Row &column multiplier having high speed in comparison to simple row & column bypass multiplier, , the experimental results show that our proposed multiplier reduces power dissipation & High speed overhead on the average for 4x4, 8x8 and 16x16 multiplier.
In this paper, based on word-serial pipeline architecture, a new efficient distributed arithmetic (NEDA) technique is introduced. This architecture increases the speed and reduced the time of 2-D discrete wavelet transform (DWT). In this design, word-serial pipeline architecture able to compute a complete 2-D discrete wavelet transforms (DWT) binary tree in an on-line fashion, and easily configurable in order to compute any required 2-D DWT sub tree is proposed. In this architecture, free of ROM, multiplication and subtraction, 9 high-pass and 7 low-pass NEDA techniques are used concurrently. The proposed NEDA architecture is 30% faster than compare the exiting architecture and 27% reduced the area. The word-serial pipelines architecture has 100% hardware utilization efficiency.
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