Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique

Abstract

In this paper, based on word-serial pipeline architecture, a new efficient distributed arithmetic (NEDA) technique is introduced. This architecture increases the speed and reduced the time of 2-D discrete wavelet transform (DWT). In this design, word-serial pipeline architecture able to compute a complete 2-D discrete wavelet transforms (DWT) binary tree in an on-line fashion, and easily configurable in order to compute any required 2-D DWT sub tree is proposed. In this architecture, free of ROM, multiplication and subtraction, 9 high-pass and 7 low-pass NEDA techniques are used concurrently. The proposed NEDA architecture is 30% faster than compare the exiting architecture and 27% reduced the area. The word-serial pipelines architecture has 100% hardware utilization efficiency.