In recent years, reversible logic has become a promising technology in the areas of low power VLSI design, nanotechnology, quantum computing and optical computing. The performance and reliability of digital systems which are now implemented using conventional logic gates can be enhanced by the usage of reversible logic gates, which pave for low power consumption and lesser quantum delays, thus increasing the speed of computation. Adder/subtractor circuits form the fundamental block in the arithmetic and logic unit of processors and other digital logic programmable devices. The performance of a digital system, its speed and throughput depend critically on the way these circuits are designed. Adder circuits are used in the Graphics Processing Unit(GPU) of computers for graphics applications to reduce complexity. Any way to enhance the performance and computational speed of these circuits will pave way for a better ALU. Incorporating the concepts of reversible computing in the design of adder/subtractor circuits can significantly enhance the performance and speed of operation of digital systems. In this paper, two existing adder/subtractor designs and a novel design are compared, analyzed for different bit lengths (1,8,16,32,64). Detailed analysis of reversible logic design parameters, power consumption parameters, and FPGA utilization parameters is carried out. These designs are analyzed and simulated using the Xilinx Vivado tool and implemented on Zedboard Zynq 7000 Evaluation and Development kit(xc7z020clg484-1). The proposed design outperforms the existing designs.
The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS
The generalized Hunter-Saxton system comprises several well-known models from fluid dynamics and serves as a tool for the study of fluid convection and stretching in one-dimensional evolution equations. In this work, we examine the global regularity of periodic smooth solutions of this system in L p , p ∈ [1, ∞), spaces for nonzero real parameters (λ, κ). Our results significantly improve/extend those by and Sarria [21]. Furthermore, we study the effects that different boundary conditions have on the global regularity of solutions by replacing periodicity with a homogeneous three-point boundary condition and establish finite-time blowup of a local-intime solution of the resulting system for particular values of the parameters.
High-performance Digital Signal Processors are the need of the hour in today's world. MAC units being integral parts of such processors are desired to consume low power and to operate at high speeds. In this paper, a detailed analysis of MAC units constructed using four different types of multipliers namely Booth, Wallace tree, array, and Vedic, is carried out. Carry Save Adder, PIPO shift register are used as the adder and the accumulator in the MAC unit. Analyzing the performance of MAC units constructed using different multipliers can help identify the optimum unit to be used in the DSP processors. These designs are constructed for three different bit lengths (4, 8, and 16) and are compared in terms of power consumption, the delay incurred, and FPGA utilization parameters like LUTs, nets, and leaf cells. These designs are analyzed and simulated using the Xilinx Vivado tool and implemented on Zedboard Zynq 7000 Evaluation and Development kit(xc7z020clg484-1).
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