SummaryIn this paper, grounded and floating decremental/incremental memristor emulators have been proposed by using an operational transconductance amplifier (OTA), current differencing buffered amplifier (CDBA), and a grounded capacitor. The proposed memristor emulators are simpler in design over most of the realizations of memristor emulators available in the literature. The proposed configurations of grounded and floating decremental memristor emulators can be easily converted into grounded and floating incremental memristor emulators. The pinched hysteresis loops obtained from proposed memristor emulators are maintained up to 1‐MHz frequency in both decremental and incremental configurations. Simulation results have been obtained using a Mentor Graphics Eldo simulation tool in 0.18‐μm complementary metal‐oxide semiconductor (CMOS) technology parameters. Analog filters have also been designed to verify the performance of proposed grounded and floating memristor emulators.
In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2[Formula: see text]MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180[Formula: see text]nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.
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