A novel capacitive sensor for measuring the water-level and monitoring the water quality has been developed in this work by using an enhanced screen printing technology. A commonly used environment-friendly conductive polymer poly(3,4-ethylenedioxythiophene):poly (styrenesulfonate) (PEDOT:PSS) for conductive sensors has a limited conductivity due to its high sheet resistance. A physical treatment performed during the printing process has reduced the sheet resistance of printed PEDOT:PSS on polyethylenterephthalat (PET) substrate from 264.39 Ω/sq to 23.44 Ω/sq. The adhesion bonding force between printed PEDOT:PSS and the substrate PET is increased by using chemical treatment and tested using a newly designed adhesive peeling force test. Using the economical conductive ink PEDOT:PSS with this new physical treatment, our capacitive sensors are cost-efficient and have a sensitivity of up to 1.25 pF/mm.
Microelectronic packaging continues the migration from wire bond to flip chip first level interconnect (FLI) to meet aggressive requirements for improved electrical performance, reduced size and weight. The interconnect pitch is being predicted by forecasts like ITRS to be reduced to 100 um and below for full array I/O layout. For wafer bumping, solder electroplating is commonly employed, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. In WLCSP, pitch and solder ball size are usually much higher and the number of I/O much lower than for Flip Chip in Package (FCiP) applications. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, encompassing FCiP to CSP bump dimensions. As the industry migrates to 300mm wafer processing and lead-free flip chip interconnect, C4NP is establishing itself as a viable solder bumping alternative. Due to its nature as a bump transfer technology, it is expected that the bumping yield will be very high, since filled molds can be inspected prior to solder transfer to the wafer. Yield is a major issue for the highest I/O applications like microprocessors. The under bump metallurgy (UBM) structure is a critical component of any solder interconnect system. The UBM typically provides three functions: adhesion to underlying dielectric and metal, barrier to protect the silicon circuitry, and a solder wettable surface
Glass is well established as wafer or panel substrate for applications like capping of image sensors or as low loss carrier for integrated passive devices. Glass substrates with higher functionality becomes more attractive for the advanced packaging due the improvement of glass processing and the increased implementation of photonic packaging which is demanded for higher data transfer rates. The through glass vias are therefore essential for the SiP and 3-D integration
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